Specifications

The key is to achieve a balanced design where the speed of the processor is
matched to that of the external components. IBM engineers achieve a balanced
design by using several techniques to reduce the
effective access time of main
system memory:
•
Cache
•
Interleaving
•
Dual path buses
•
SynchroStream technology
1.3.1 Caches
Research has shown that when a system uses data, it will be likely to use it
again. As previously discussed, the faster the access to this data occurs, the
faster the overall machine will operate. Caches are memory buffers that act as
temporary storage places for instructions and data obtained from slower, main
memory. They use static RAM and are much faster than the dynamic RAM used
for system memory (typically five to ten times faster). However, SRAM is more
expensive and requires more power, which is why it is not used for all memory.
Caches reduce the number of clock cycles required for a memory access since
they are implemented with fast SRAMs. Whenever the processor must perform
external memory read accesses, the cache controller always pre-fetches extra
bytes and loads them into the cache. When the processor needs the next piece
of data, it is likely that it is already in the cache. If so, processor performance is
enhanced, if not, the penalty is minimal.
Caches are cost-effective because they are relatively small as compared to the
amount of main memory.
There are several levels of cache implemented in IBM PC servers. The cache
incorporated into the main system processor is known as Level 1 (L1) cache.
The Intel 486 incorporates a single 8KB cache. The Intel Pentium family has two
8KB caches, one for instructions and one for data. Access to these on-board
caches are very fast and consume only a fraction of the time required to access
memory locations external to the chip.
The second level of cache, called second-level cache or L2 cache, provides
additional high speed memory to the L1 cache. If the processor cannot find what
it needs in the processor cache (a first-level
cache miss ), it then looks in the
additional cache memory. If it finds the code or data there (a second-level
cache
hit
) the processor will use it and continue. If the data is in neither of the caches,
an access to main memory must occur.
L2 caches are standard in all IBM PC server models.
With all types of caching, more is not always better. Depending on the system,
the optimum size of Level 2 Cache is usually 128KB to 512KB.
L2 Caches can be of two types:
•
Write-Through Cache
Read operations are issued from the cache but write operations are sent
directly to the standard memory. Performance improvements are obtained
only for read operations.
4 NetWare Integration Guide