Installation guide

IBM Eserver xSeries 366 Technical Introduction 9
32-bit process on this system gets its very own 4 GB of physical memory space
(provided sufficient physical memory is installed). This is already a huge improvement
compared to IA32, where the operating system kernel and the application had to share
4 GB of physical memory.
Additionally, the compatibility mode does not support the virtual 8086 mode, so
real-mode legacy applications are not supported. However, 16-bit protected mode
applications are supported.
– Full 64-bit mode
The final mode is the full 64-bit mode. Intel refers to it as the
IA-32e mode (AMD refers
to this as the
long mode). This mode is applied when a 64-bit operating system and
64-bit application are used. In the full 64-bit operating mode, an application can have a
virtual address space of up to 40 bits (which equates to 1 TB of addressable memory).
The amount of physical memory is determined by how many DIMM slots the server has
and the maximum DIMM capacity supported and available at the time.
Applications that run in full 64-bit mode will have access to the full physical memory
range (depending on the operating system), and to the new GPRs and the expanded
GPRs. However, it is important to understand that this mode of operation requires not
only a 64-bit operating system (and, of course, 64-bit drivers) but also a 64-bit
application that has been recompiled to take full advantage of the various
enhancements of the 64-bit addressing architecture.
For more information about the features of the Xeon Processor MP, refer to:
http://www.intel.com/design/Xeon/xeonmp/prodbref/
For more information about EM64T, see:
http://www.intel.com/technology/64bitextensions/
XceL4v Dynamic Server Cache
An XceL4 Dynamic Server Cache serves two purposes in the X3 Architecture servers (the
x260, x366, and x460):
򐂰 A snoop filter lookup table to reduce traffic on the front side bus (all three servers)
򐂰 A cache for multi-node configurations to reduce latency across the scalability cables in
x460 configurations (x460 servers only)
With advances in chip design, IBM has now reduced the latency of main memory to below
that of the XceL4 cache in the x445. In other words, the time it takes to access data directly
from memory is almost as fast as accessing it from L3. As a result, on a four-way system such
as the x366, there is little or no need for either a L3 cache or L4 cache (as implemented in the
XceL4v).
Since the L3 cache is inline, when cache misses do occur, it adds significant overhead to
memory access. The L3 cache rate has to be very high for it to keep up with the 3.66 GHz
processor. In most server applications with multiple users, the threads competing for L3
cache generate a lower hit rate, and the latency of the L3 drops performance. The same
applies to any L4 cache.
As a result, there is no performance benefit in implementing neither L3 nor L4 cache on the
four-way x366. For these reasons there is 0 MB of XceL4v cache on the x366 server.