Installation guide

6 IBM Eserver xSeries 366 Technical Introduction
Figure 5 x366 processor tray
The “Cranford” Xeon MP processor has two levels of cache on the processor die:
򐂰 L2 cache is 1 MB in size. The L2 cache implements the Advanced Transfer Cache
technology, which means L2-to-processor transfers occur across a 256-bit bus in only one
clock cycle.
򐂰 L1 execution trace cache is used to store micro-operations (that is, decoded executable
machine instructions); it serves those to the processor at rated speed. This additional level
of cache saves decode time on cache hits.
Key features of the processors used in the x366 include:
򐂰 667 MHz front-side bus
The Pentium® III Xeon processor in older servers had a 100 MHz front-side bus that
equated a burst throughput of 800 MBps. With protocols such as TCP/IP, this has been
shown to be a bottleneck in high-throughput situations.
The “Cranford” Xeon Processor MP improves on this by using two 133 MHz clocks, out of
phase with each other by 90° and using both edges of each clock to transmit data. This is
shown in Figure 6.
Figure 6 Quad-pumped frontside bus
This increases the performance of the frontside bus without the difficulty of high-speed
clock signal integrity issues. Because the bus is 8 bytes wide, the end result is an effective
burst throughput of 5.33 GBps, which can have a substantial impact, especially on
TCP/IP-based LAN traffic.
FRON
T
FRONT
FRO
NT
1
2
3
4
The processor tray pulls out
from the front of the server
and houses the CPUs,
VRMs, and memory
controller.
133 MHz clock A
133 MHz clock B