Datasheet

MAX98357A/MAX98357B
PCM Input Class D Audio Power Amplifiers
17Maxim Integrated
cally enter standby mode. In standby mode, the Class
D speaker is turned off and the outputs go into a high-
impedance state, ensuring that unwanted current is not
transferred to the load during this condition. Standby
mode has reduced power consumption from normal
operation (340µA), but does not reach as low as full
shutdown (0.6µA). Standby mode can be used to reduce
power consumption when no GPIO us available to pull
SD_MODE low.
DAC Digital Filters
The DAC features a digital lowpass filter that is automati-
cally configured for voice playback or music playback
based on the sample rate that is used. This filter elimi-
nates the effect of aliasing and any other high-frequency
noise that might otherwise be present. Table 4 shows the
digital filter settings that are automatically selected.
SD_MODE and Shutdown Operation
The ICs feature a low-power shutdown mode, drawing
less than 0.6FA (typ) of supply current. During shutdown,
all internal blocks are turned off, including setting the
output stage to a high-impedance state. Drive SD_MODE
low to put the ICs into shutdown.
The state of SD_MODE determines the audio channel
that is sent to the amplifier output (Table 5).
Drive SD_MODE high to select the left word of the stereo
input data. Drive SD_MODE high through a sufficiently
small resistor to select the right word of the stereo input
data. Drive SD_MODE high through a sufficiently large
resistor to select both the left and right words of the
stereo input data (left/2 + right/2). R
LARGE
and R
SMALL
are determined by the V
DDIO
voltage (logic voltage from
control interface) that is driving SD_MODE according to
the following two equations:
R
SMALL
(kI) = 94.0 x V
DDIO
- 100
R
LARGE
(kI) = 222.2 x V
DDIO
- 100
When the devices are configured in left-channel mode
(SD_MODE is directly driven to logic-high by the con-
trol interface), take care to avoid violating the Absolute
Maximum Ratings limits for SD_MODE. Ensuring that
V
DD
is always greater than V
DDIO
is one way to prevent
SD_MODE from violating the Absolute Maximum Ratings
limits. If this is not possible in the application (e.g., if V
DD
< 3.0V and V
DDIO
= 3.3V), then it is necessary to add a
small resistance (~2kI) in series with SD_MODE to limit
the current into the SD_MODE pin. This is not a concern
when using the right channel or (left/2 + right/2) modes.
Figure 4 and Figure 5 show how to connect an external
resistor to SD_MODE when using an open-drain driver or
a push-pull driver.
Table 4. Digital Filter Settings
Table 5. SD_MODE Control
Table 6. Examples of SD_MODE Pullup Resistor Values
LRCLK
FREQUENCY
-3dB CUTOFF
FREQUENCY
RIPPLE LIMIT CUTOFF
FREQUENCY
STOPBAND CUTOFF
FREQUENCY
STOPBAND
ATTENUATION (dB)
f
LRCLK
< 30kHz 0.446 x f
LRCLK
0.443 x f
LRCLK
0.464 x f
LRCLK
75
30kHz < f
LRCLK
< 50kHz 0.47 x f
LRCLK
0.43 x f
LRCLK
0.58 x f
LRCLK
60
f
LRCLK
> 50kHz 0.31 x f
LRCLK
0.24 x f
LRCLK
0.477 x f
LRCLK
60
SD_MODE STATUS
SELECTED CHANNEL
High
V
SD_MODE
> B2 trip point
Left
Pullup through R
SMALL
B2 trip point > V
SD_MODE
> B1 trip point
Right
Pullup through R
LARGE
B1 trip point > V
SD_MODE
> B0 trip point
(Left/2 + right/2)
Low
B0 trip point > V
SD_MODE
Shutdown
LOGIC VOLTAGE LEVEL (V
DDIO
) (V)
R
SMALL
(kI) R
LARGE
(kI)
1.8 69.8 300
3.3 210.2 634