Datasheet

MAX98357A/MAX98357B
PCM Input Class D Audio Power Amplifiers
16Maxim Integrated
Detailed Description
The MAX98357A/MAX98357B are digital PCM input
Class D power amplifiers. The MAX98357A accepts
standard I
2
S data through DIN, BCLK, and LRCLK while
the MAX98357B accepts left-justified data through the
same inputs. Both versions also accept 16-bit or 32-bit
TDM data with up to eight slots. The digital audio inter-
face eliminates the need for an external MCLK signal that
is typically required for I
2
S data transmission.
SD_MODE selects which data word is output by the
amplifier and is used to put the ICs into shutdown. These
devices offer five gain settings in I
2
S/left-justified mode
and a fixed 12dB gain in TDM mode. Channel selection
in TDM mode is set with the combination of SD_MODE
and GAIN_SLOT (Table 7).
The MAX98357A/MAX98357B feature low-quiescent cur-
rent, comprehensive click-and-pop suppression, and
excellent RF immunity. The ICs offer Class AB audio
performance with Class D efficiency in a minimal board-
space solution. The Class D amplifier features spread-
spectrum modulation with edge-rate and overshoot
control circuitry that offers significant improvements in
switch-mode amplifier radiated emissions. The amplifier
features click-and-pop suppression that reduces audi-
ble transients on startup and shutdown. The amplifier
includes thermal-overload and short-circuit protection.
Digital Audio Interface Modes
The input stage of the digital audio interface is highly flexi-
ble, supporting 8kHz–96kHz sampling rates with 16/24/32-
bit resolution for I
2
S/left justified data as well as up to a
8-slot, 16-bit or 32-bit time division multiplexed (TDM)
format. When LRCLK has a 50% duty cycle the data
format is determined by the part number selection
(MAX98357A/MAX98357B). When a frame sync pulse
is used for the LRCLK the data format is automatically
configured in TDM mode. The frame sync pulse indicates
the beginning of the first time slot.
MCLK Elimination
The ICs eliminate the need for the external MCLK sig-
nal that is typically used for PCM communication. This
reduces EMI and possible board coupling issues in addi-
tion to reducing the size and pin-count of the ICs.
BCLK Jitter Tolerance
The ICs feature a BCLK jitter tolerance of 0.5ns for RMS
jitter below 40kHz and 12ns for wideband RMS jitter while
maintaining a dynamic range greater than 98dB (Table 1).
BCLK Polarity
When operating in I
2
S/left justified mode, incoming serial
data is always clocked-in on the rising edge of BCLK.
In TDM mode, the MAX98357A clocks-in serial data on
the rising edge of BCLK while the MAX98357B clocks in
serial data on the falling edge of BCLK (Table 2).
LRCLK Polarity
LRCLK specifies whether left-channel data or right-
channel data is currently being read by the digital audio
interface. The MAX98357A indicates the left channel
word when LRCLK is low, and the MAX98357B indicates
the left channel word when LRCLK is high (Table 3).
LRCLK ONLY supports 8kHz, 16kHz, 32kHz, 44.1kHz,
48kHz, 88.2kHz and 96kHz frequencies. LRCLK clocks at
11.025kHz, 12kHz, 22.05kHz and 24kHz are NOT sup-
ported. Do not remove LRCLK while BCLK is present.
Removing LRCLK while BCLK is present can cause unex-
pected output behavior including a large DC output voltage.
Standby Mode
The ICs automatically enter standby mode when BCLK
is removed. If BCLK stops toggling, the ICs automati-
Table 1. RMS Jitter Tolerance
Table 2. BCLK Polarity
Table 3. LRCLK Polarity
FREQUENCY RMS JITTER TOLERANCE (ns)
< 40kHz 0.5
40kHz–BCLK 12
MODE PART NUMBER BCLK POLARITY
I
2
S MAX98357A Rising edge
Left-justified MAX98357B Rising edge
TDM
MAX98357A Rising edge
MAX98357B Falling edge
PART NUMBER LRCLK POLARITY (LEFT CHANNEL)
MAX98357A Low
MAX98357B High