Datasheet

Notice you tell the configure_integer function both the PLL to use and the integer divider value. You can point at either

of the pll_a or pll_b objects on the Si5351 to use a specific PLL as the source.

The final frequency set by the clock will then be configured as the PLL source frequency (500 MHz here) divided by

the divider value (4), or 125 MHz. You can check by reading the frequency property of the clock:

Like the PLL configuration you can also set a fractional divider with the configure_fractional function on the clock. Let's

set clock 1 to have PLL B as the source and a divider of 4.5:

If you do the math you should expect a source PLL of 512.5 MHz divided by 4.5 would yield a clock output of 113.8889

MHz. Check the frequency property to be sure:

Enabling Outputs

There's one last thing to do before the clock outputs will actually work, you need to enable them. You can enable all

the clock outputs by setting the outputs_enabled property to True :

Now the clock 0, 1, 2 outputs should output a square wave at the configured frequency based on their PLL and

multipliers & dividers. You might need to use an oscilloscope that's very fast to measure some of these outputs as the

Si5351 can generate quite high clockspeeds well above 100 MHz!

If you want to disable the outputs set outputs_enabled to False .

That's all there is to using the Si5351 clock generator with CircuitPython! Here's a complete example that will

configure all 3 clocks in various ways. Save this as code.py on your board and read the comments to see how it

configures each clock.

Full Example Code

print('Clock 0: {0:0.3f} MHz'.format(si5351.clock_0.frequency/1000000))

si5351.clock_1.configure_fractional(si5351.pll_b, 4, 1, 2)

print('Clock 1: {0:0.3f} MHz'.format(si5351.clock_1.frequency/1000000))

si5351.outputs_enabled = True

# Simple demo of the SI5351 clock generator.

# This is like the Arduino library example:

# https://github.com/adafruit/Adafruit_Si5351_Library/blob/master/examples/si5351/si5351.ino

# Which will configure the chip with:

# - PLL A at 900mhz