Datasheet

Don't forget, if you read the datasheet you'll see the Si5351 only supports a PLL multiple of 15-90!

If you're curious you can read the frequency property of the PLL to read back what frequency it is configured to use:

The other way to configure a PLL is with a fractional multiplier. This allows you to set both the integer multiple and a

fractional multiple (specified by a numerator and denominator). Fractional multipliers can let you specify an even

greater range of frequencies, but they might not be accurate and could be susceptible to jitter over time.

For example to configure PLL B to 512.5 MHz you can specify a multiplier of 20.5 by calling:

Notice the configure_fractional function takes in again the integer multiple (20) but also adds a numerator (1) and

denominator (2) value. The actual multiplier will be the combination of the integer multiplier plus the

numerator/denominator. In this case 20.5 or 20 1/2 is the multiplier.

Again you can read the frequency property to confirm the value that was set.

Configure Clock Outputs

Once a PLL is configured you can then configure any of the three clock outputs of the Si5351. Each clock output is fed

in a PLL as input and will divide it down to a final frequency value. Any PLL can be plugged in to any clock output, but

remember you only have two PLLs to configure and use.

Each of the clocks is exposed on the SI5351 object:

clock_0 The clock 0 output.

clock_1 The clock 1 output.

clock_2 The clock 2 output.

Just like configuring the PLLs you can configure the clock divider with a configure_integer and configure_fractional

function. Again the same trade-off of precision vs. range applies for integer vs. fractional dividers applies. For

example to set clock 0 to use PLL A as a source (running at 500 MHz as configured above) and a divider of 4 you