Datasheet

Set up the PLL with 'integer mode'

The cleanest way to run the PLL is to do a straight up integer multiplication:

This sets PLL_A or PLL_B to be 25MHz * m and m (the integer multipler) can range from 15 to 90!

Set up the PLL with 'fractional mode'

This mode allows a much more flexible PLL setting by using fractional multipliers for the PLL setup, however, the

output may have a slight amount of jitter so if possible, try to use integer mode!

This sets PLL_A or PLL_B to be 25MHz * (m + n/d)

m (the integer multipler) can range from 15 to 90

n (the numerator) can range from 0 to 1,048,575

d (the denominator) can range from 1 to 1,048,575

Set up the clock divider

Once you have the PLLs set up, you can now divide that high frequency down to get the number you want for the

output

Each output has its own divider. You can use the cleaner Integer-only divider:

For the output use 0, 1 or 2

For the PLL input, use either SI5351_PLL_A or SI5351_PLL_B

For the divider, you can divide by SI5351_MULTISYNTH_DIV_4, SI5351_MULTISYNTH_DIV_6, or

SI5351_MULTISYNTH_DIV_8

Again, integer output will give you the cleanest clock. If you need more flexibility, use the fractional generator/divider:

For the output use 0, 1 or 2

For the PLL input, use either SI5351_PLL_A or SI5351_PLL_B

The final frequency is equal to the PLL / (div + n/d)

div can range from 4 to 900

n can range from 0 to 1,048,575

d can range from 1 to 1,048,575

Additional R Divider

If you need to divide even more, to get to the < 100 KHz frequencies, there's an additional R divider, that divides the

output once more by a fixed number:

clockgen.setupPLLInt(SI5351_PLL_A or SI5351_PLL_B, m);

clockgen.setupPLLInt(SI5351_PLL_A or SI5351_PLL_B, m, n, d);

clockgen.setupMultisynthInt(output, SI5351_PLL_x, SI5351_MULTISYNTH_DIV_x);

clockgen.setupMultisynth(output, SI5351_PLL_x, div, n, d);