Datasheet
MMA8451Q
Sensors
46 Freescale Semiconductor, Inc.
Table 74. MMA8451Q Register Map
Reg Name Definition Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00 STATUS/F_STATUS Data Status R ZYXOW ZOW YOW XOW ZYXDR ZDR YDR XDR
01 OUT_X_MSB 14 bit X Data R XD13 XD12 XD11 XD10 XD9 XD8 XD7 XD6
02 OUT_X_LSB 14 bit X Data R XD5 XD4 XD3 XD2 XD1 XD0 0 0
03 OUT_Y_MSB 14 bit Y Data R YD13 YD12 YD11 YD10 YD9 YD8 YD7 YD6
04 OUT_Y_LSB 14 bit Y Data R YD5 YD4 YD3 YD2 YD1 YD0 0 0
05 OUT_Z_MSB 14 bit Z Data R ZD13 ZD12 ZD11 ZD10 ZD9 ZD8 ZD7 ZD6
06 OUT_Z_LSB 14 bit Z Data R ZD5 ZD4 ZD3 ZD2 ZD1 ZD0 0 0
09 F_SETUP FIFO Setup R/W F_MODE1 F_MODE0 F_WMRK5 F_WMRK4 F_WMRK3 F_WMRK2 F_WMRK1 F_WMRK0
0A TRIG_CFG FIFO Triggers R/W — — Trig_TRANS Trig_LNDPRT Trig_PULSE Trig_FF_MT — —
0B SYSMOD System Mode R FGERR FGT_4 FGT_3 FGT_2 FGT_1 FGT_0 SYSMOD1 SYSMOD0
0C INT_SOURCE Interrupt Status R SRC_ASLP SRC_FIFO SRC_TRANS SRC_LNDPRT SRC_PULSE SRC_FF_MT — SRC_DRDY
0D WHO_AM_I ID Register R 0 0 0 1 1 0 1 0
0E XYZ_DATA_CFG Data Config R/W — — — HPF_Out — — FS1 FS0
0F HP_FILTER_CUTOFF HP Filter Setting R/W — — Pulse_HPF_BYP Pulse_LPF_EN — — SEL1 SEL0
10 PL_STATUS PL Status R NEWLP LO — — — LAPO[1] LAPO[0] BAFRO
11 PL_CFG PL Configuration R/W DBCNTM PL_EN — — — — — —
12 PL_COUNT PL DEBOUNCE R/W DBNCE[7] DBNCE[6] DBNCE[5] DBNCE[4] DBNCE[3] DBNCE[2] DBNCE[1] DBNCE[0]
13 PL_BF_ZCOMP
PL Back/Front Z Comp
R/W
BKFR[1] BKFR[0] — — — ZLOCK[2] ZLOCK[1] ZLOCK[0]
14 P_L_THS_REG PL THRESHOLD R/W P_L_THS[4] P_L_THS[3] P_L_THS[2] P_L_THS[1] P_L_THS[0] HYS[2] HYS[1] HYS[0]
15 FF_MT_CFG
Freefall/Motion Config
R/W
ELE OAE ZEFE YEFE XEFE — — —
16 FF_MT_SRC
Freefall/Motion Source
R
EA — ZHE ZHP YHE YHP XHE XHP
17 FF_MT_THS
Freefall/Motion Threshold
R/W
DBCNTM THS6 THS5 THS4 THS3 THS2 THS1 THS0
18 FF_MT_COUNT
Freefall/Motion Debounce
R/W
D7 D6 D5 D4 D3 D2 D1 D0
1D TRANSIENT_CFG Transient Config R/W — — — ELE ZTEFE YTEFE XTEFE HPF_BYP
1E TRANSIENT_SRC Transient Source R — EA ZTRANSE Z_Trans_Pol YTRANSE Y_Trans_Pol XTRANSE X_Trans_Pol
1F TRANSIENT_THS Transient Threshold R/W DBCNTM THS6 THS5 THS4 THS3 THS2 THS1 THS0
20 TRANSIENT_COUNT
Transient Debounce
R/W
D7 D6 D5 D4 D3 D2 D1 D0
21 PULSE_CFG Pulse Config R/W DPA ELE ZDPEFE ZSPEFE YDPEFE YSPEFE XDPEFE XSPEFE
22 PULSE_SRC Pulse Source R EA AxZ AxY AxX DPE Pol_Z Pol_Y Pol_X
23 PULSE_THSX Pulse X Threshold R/W — THSX6 THSX5 THSX4 THSX3 THSX2 THSX1 THSX0
24 PULSE_THSY Pulse Y Threshold R/W — THSY6 THSY5 THSY4 THSY3 THSY2 THSY1 THSY0
25 PULSE_THSZ Pulse Z Threshold R/W — THSZ6 THSZ5 THSZ4 THSZ3 THSZ2 THSZ1 THSZ0
26 PULSE_TMLT Pulse First Timer R/W TMLT7 TMLT6 TMLT5 TMLT4 TMLT3 TMLT2 TMLT1 TMLT0
27 PULSE_LTCY Pulse Latency R/W LTCY7 LTCY6 LTCY5 LTCY4 LTCY3 LTCY2 LTCY1 LTCY0
28 PULSE_WIND
Pulse 2nd Window
R/W
WIND7 WIND6 WIND5 WIND4 WIND3 WIND2 WIND1 WIND0
29 ASLP_COUNT
Auto-SLEEP Counter
R/W
D7 D6 D5 D4 D3 D2 D1 D0
2A CTRL_REG1 Control Reg1 R/W ASLP_RATE1 ASLP_RATE0 DR2 DR1 DR0 LNOISE F_READ ACTIVE
2B CTRL_REG2 Control Reg2 R/W ST RST — SMODS1 SMODS0 SLPE MODS1 MODS0
2C CTRL_REG3
Control Reg3
(WAKE Interrupts from
SLEEP) R/W
FIFO_GATE WAKE_TRANS WAKE_LNDPRT WAKE_PULSE WAKE_FF_MT — IPOL PP_OD
2D CTRL_REG4
Control Reg4
(Interrupt Enable Map)
R/W
INT_EN_ASLP INT_EN_FIFO INT_EN_TRANS INT_EN_LNDPRT INT_EN_PULSE INT_EN_FF_MT — INT_EN_DRDY
2E CTRL_REG5
Control Reg5
(Interrupt Configuration)
R/W
INT_CFG_ASLP INT_CFG_FIFO INT_CFG_TRANS INT_CFG_LNDPRT INT_CFG_PULSE INT_CFG_FF_MT — INT_CFG_DRDY
2F OFF_X X 8-bit offset R/W D7 D6 D5 D4 D3 D2 D1 D0
30 OFF_Y Y 8-bit offset R/W D7 D6 D5 D4 D3 D2 D1 D0
31 OFF_Z Z 8-bit offset R/W D7 D6 D5 D4 D3 D2 D1 D0