Datasheet

MMA8451Q
Sensors
24 Freescale Semiconductor, Inc.
0x0A: TRIG_CFG
In the trigger configuration register the bits that are set (logic ‘1’) control which function may trigger the FIFO to its interrupt
and conversely bits that are cleared (logic ‘0’) indicate which function has not asserted its interrupt.
The bits set are rising edge sensitive, and are set by a low to high state change and reset by reading the appropriate source
register.
0x0B: SYSMOD System Mode Register
The System mode register indicates the current device operating mode. Applications using the Auto-SLEEP/WAKE
mechanism should use this register to synchronize the application with the device operating mode transitions. The System mode
register also indicates the status of the FIFO gate error and number of samples since the gate error occurred.
0x0A: TRIG_CFG Trigger Configuration Register (Read/Write)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
— — Trig_TRANS Trig_LNDPRT Trig_PULSE Trig_FF_MT — —
Table 17. Trigger Configuration Description
INT_SOURCE Description
Trig_TRANS Transient interrupt trigger bit. Default value: 0
Trig_LNDPRT Landscape/Portrait Orientation interrupt trigger bit. Default value: 0
Trig_PULSE Pulse interrupt trigger bit. Default value: 0
Trig_FF_MT Freefall/Motion trigger bit. Default value: 0
0x0B: SYSMOD: System Mode Register (Read Only)
Bit
7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FGERR FGT_4 FGT_3 FGT_2 FGT_1 FGT_0 SYSMOD1 SYSMOD0
Table 18. SYSMOD Description
FGERR
FIFO Gate Error. Default value: 0.
0: No FIFO Gate Error detected.
1: FIFO Gate Error was detected.
Emptying the FIFO buffer clears the FGERR bit in the SYS_MOD register.
See section 0x2C: CTRL_REG3 Interrupt Control Register for more information on configuring the FIFO Gate function.
FGT[4:0] Number of ODR time units since FGERR was asserted. Reset when FGERR Cleared. Default value: 0_0000
SYSMOD[1:0]
System Mode. Default value: 00.
00: STANDBY mode
01: WAKE mode
10: SLEEP mode