Datasheet
MMA8451Q
Sensors
44 Freescale Semiconductor, Inc.
0x2C: CTRL_REG3 Interrupt Control Register
IPOL bit selects the polarity of the interrupt signal. When IPOL is ‘0’ (default value) any interrupt event will signaled with a
logical 0.
PP_OD bit configures the interrupt pin to Push-Pull or in Open Drain mode. The default value is 0 which corresponds to Push-
Pull mode. The Open Drain configuration can be used for connecting multiple interrupt signals on the same interrupt line.
0x2D: CTRL_REG4 Register (Read/Write)
The corresponding functional block interrupt enable bit allows the functional block to route its event detection flags to the
system’s interrupt controller. The interrupt controller routes the enabled functional block interrupt to the INT1 or INT2 pin.
0x2C: CTRL_REG3 Register (Read/Write)
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
FIFO_GATE WAKE_TRANS WAKE_LNDPRT WAKE_PULSE WAKE_FF_MT — IPOL PP_OD
Table 68. CTRL_REG3 Description
FIFO_GATE
0: FIFO gate is bypassed. FIFO is flushed upon the system mode transitioning from WAKE to SLEEP mode or from SLEEP
to WAKE mode. Default value: 0.
1: The FIFO input buffer is blocked when transitioning from WAKE to SLEEP mode or from SLEEP to WAKE mode until the
FIFO is flushed. Although the system transitions from WAKE to SLEEP or from SLEEP to WAKE the contents of the FIFO
buffer are preserved, new data samples are ignored until the FIFO is emptied by the host application.
If the FIFO_GATE bit is set to logic ‘1’ and the FIFO buffer is not emptied before the arrival of the next sample, then the
FGERR bit in the SYS_MOD register (0x0B) will be asserted. The FGERR bit remains asserted as long as the FIFO buffer
remains un-emptied.
Emptying the FIFO buffer clears the FGERR bit in the SYS_MOD register.
WAKE_TRANS
0: Transient function is bypassed in SLEEP mode. Default value: 0.
1: Transient function interrupt can wake up system
WAKE_LNDPRT
0: Orientation function is bypassed in SLEEP mode. Default value: 0.
1: Orientation function interrupt can wake up system
WAKE_PULSE
0: Pulse function is bypassed in SLEEP mode. Default value: 0.
1: Pulse function interrupt can wake up system
WAKE_FF_MT
0: Freefall/Motion function is bypassed in SLEEP mode. Default value: 0.
1: Freefall/Motion function interrupt can wake up
IPOL
Interrupt polarity ACTIVE high, or ACTIVE low. Default value: 0.
0: ACTIVE low; 1: ACTIVE high
PP_OD
Push-Pull/Open Drain selection on interrupt pad. Default value: 0.
0: Push-Pull; 1: Open Drain
0x2D: CTRL_REG4 Register (Read/Write)
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
INT_EN_ASLP INT_EN_FIFO INT_EN_TRANS INT_EN_LNDPR INT_EN_PULSE INT_EN_FF_MT — INT_EN_DRDY
Table 69. Interrupt Enable Register Description
Interrupt Enable
Descript
i
on
INT_EN_ASLP
Interrupt Enable. Default value: 0.
0: Auto-SLEEP/WAKE interrupt disabled; 1: Auto-SLEEP/WAKE interrupt enabled.
INT_EN_FIFO
Interrupt Enable. Default value: 0.
0: FIFO interrupt disabled; 1: FIFO interrupt enabled.
INT_EN_TRANS
Interrupt Enable. Default value: 0.
0: Transient interrupt disabled; 1: Transient interrupt enabled.
INT_EN_LNDPRT
Interrupt Enable. Default value: 0.
0: Orientation (Landscape/Portrait) interrupt disabled.
1: Orientation (Landscape/Portrait) interrupt enabled.
INT_EN_PULSE
Interrupt Enable. Default value: 0.
0: Pulse Detection interrupt disabled; 1: Pulse Detection interrupt enabled
INT_EN_FF_MT
Interrupt Enable. Default value: 0.
0: Freefall/Motion interrupt disabled; 1: Freefall/Motion interrupt enabled
INT_EN_DRDY
Interrupt Enable. Default value: 0.
0: Data Ready interrupt disabled; 1: Data Ready interrupt enabled