Datasheet
Datasheet - Apr. 2013 - ams163.5 TSL2591 – 7
The timing characteristics of TSL2591 are given below.
Figure TSL2591 – 10:
AC Electrical Characteristics, V
DD
= 3 V, T
A
= 25ºC (unless otherwise noted)
† Specied by design and characterization; not production tested.
Figure TSL2591 – 11:
Parameter Measurement Information
Parameter
†
Description Min Typ Max Units
f
(SCL)
Clock frequency (I
2
C only)
0 400 kHz
t
(BUF)
Bus free time between start and stop
condition
1.3 µs
t
(HDSTA)
Hold time after (repeated) start
condition. After this period, the first
clock is generated.
0.6 µs
t
(SUSTA)
Repeated start condition setup time 0.6 µs
t
(SUSTO)
Stop condition setup time 0.6 µs
t
(HDDAT)
Data hold time 0 µs
t
(SUDAT)
Data setup time 100 ns
t
(LOW)
SCL clock low period 1.3 µs
t
(HIGH)
SCL clock high period 0.6 µs
t
F
Clock/data fall time 300 ns
t
R
Clock/data rise time 300 ns
C
i
Input pin capacitance 10 pF
Timing Characteristics
Timing Diagrams