Datasheet

HMC5883L
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REGISTERS
This device is controlled and configured via a number of on-chip registers, which are described in this section. In the
following descriptions, set implies a logic 1, and reset or clear implies a logic 0, unless stated otherwise.
Register List
The table below lists the registers and their access. All address locations are 8 bits.
Address Location
Name
Access
00
Configuration Register A
Read/Write
01
Configuration Register B
Read/Write
02
Mode Register
Read/Write
03
Data Output X MSB Register
Read
04
Data Output X LSB Register
Read
05
Data Output Z MSB Register
Read
06
Data Output Z LSB Register
Read
07
Data Output Y MSB Register
Read
08
Data Output Y LSB Register
Read
09
Status Register
Read
10
Identification Register A
Read
11
Identification Register B
Read
12
Identification Register C
Read
Table2: Register List
Register Access
This section describes the process of reading from and writing to this device. The devices uses an address pointer to
indicate which register location is to be read from or written to. These pointer locations are sent from the master to this
slave device and succeed the 7-bit address (0x1E) plus 1 bit read/write identifier, i.e. 0x3D for read and 0x3C for write.
To minimize the communication between the master and this device, the address pointer updated automatically without
master intervention. The register pointer will be incremented by 1 automatically after the current register has been read
successfully.
The address pointer value itself cannot be read via the I
2
C bus.
Any attempt to read an invalid address location returns 0’s, and any write to an invalid address location or an undefined bit
within a valid address location is ignored by this device.
To move the address pointer to a random register location, first issue a “write” to that register location with no data byte
following the commend. For example, to move the address pointer to register 10, send 0x3C 0x0A.