Datasheet

REGISTER CONFIGURATION
¼
¼
¼
Grayscale ShiftRegister(12Bits 24Channels)´Data
GrayscaleDataLatch(12Bits 24Channels)´
288Bits
ToPWMTimingControlBlock
¼
¼ ¼
SOUT
GSDataforOUT23 GSDataforOUT22 GSDataforOUT1¼
GSDataforOUT0
MSB
287
276 275
12 11
LSB
0
GSDatafor
Bit0ofOUT1
GSDatafor
Bit11of
OUT0
GSDatafor
Bit0ofOUT0
GSDatafor
Bit0of
OUT23
GSDatafor
Bit11of
OUT22
GSDatafor
Bit11of
OUT23
SIN
SCLK
¼
¼ ¼
GSDataforOUT23 GSDataforOUT22 GSDataforOUT1¼
GSDataforOUT0
MSB
287
276 275
12 11
LSB
0
GSDatafor
Bit0ofOUT1
GSDatafor
Bit11of
OUT0
GSDatafor
Bit0ofOUT0
GSDatafor
Bit0of
OUT23
GSDatafor
Bit11of
OUT22
GSDatafor
Bit11of
OUT23
XLAT
TLC5947
www.ti.com ................................................................................................................................................. SBVS114A – JULY 2008 – REVISED SEPTEMBER 2008
The TLC5947 has a grayscale (GS) data shift register and data latch. Both the GS data shift register and latch
are 288 bits long and are used to set the PWM timing for the constant current driver. Table 2 shows the on duty
cycle for each GS data. Figure 19 shows the shift register and data latch configuration. The data at the SIN pin
are shifted to the LSB of the shift register at the rising edge of the SCLK pin; SOUT data are shifted out on the
falling edge of SCLK. The timing diagram for data writing is shown in Figure 20 . The driver on duty is controlled
by the data in the GS data latch.
Figure 19. Grayscale Data Shift Register and Latch Configuration
Table 2. GS Data versus On Duty
GS DATA GS DATA GS DATA DUTY OF DRIVER TURN-ON
(Binary) (Decimal) (Hex) TIME (%)
0000 0000 0000 0 000 0.00
0000 0000 0001 1 001 0.02
0000 0000 0010 2 002 0.05
0000 0000 0011 3 003 0.07
— — — —
0111 1111 1111 2047 7FF 49.98
1000 0000 0000 2048 800 50.00
1000 0000 0001 2049 801 50.02
— — — —
1111 1111 1101 4093 FFD 99.93
1111 1111 1110 4094 FFE 99.95
1111 1111 1111 4095 FFF 99.98
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