Datasheet

Digital interfaces LSM303DLHC
18/42 Doc ID 018771 Rev 1
5 Digital interfaces
The registers embedded inside the LSM303DLHC are accessible through two separate I
2
C
serial interfaces, one for the accelerometer core and one for the magnetometer core.
5.1 I
2
C serial interface
The LSM303DLHC I
2
C is a bus slave. The I
2
C is employed to write the data into the
registers whon also be read back.
The relevant I
2
C terminology is given in the table below.
There are two signals associated with the I
2
C bus, the serial clock line (SCL) and the serial
data line (SDA). The latter is a bidirectional line used for sending and receiving the data
to/from the interface.
Table 9. Serial interface pin description
PIN Name PIN Description
SCL I
2
C serial clock (SCL)
SDA I
2
C serial data (SDA)
Table 10. Serial interface pin description
Term Description
Transmitter The device which sends data to the bus
Receiver The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals, and terminates a
transfer
Slave The device addressed by the master