Specifications

VSBC-6862 Rev 1.43
90
6.2. Reset Word
The ResetWord is a 32 bits field read by the PowerQUICC II during Power-On sequence. This word
set several important options for the hardware operations.
The Reset Word must be located in the bootable device, on the VSBC-6862, it will be in the Flash
memory bank, at offset 0.
For the VSBC-6862, the ResetWord is recommended as:
Bit Field Value Function
0 EARB
0
Arbitration: internal
1 EXMC
0
Memory controller: internal
2 CDIS
0
Core: active
3 EBM
0
Bus mode: MPC-8260 mode
4-5 BPS
11
Boot port size: 32 bits
6 CIP 1 Exceptions addresses: $000n nnnn
7 ISPS 0 Internal space port size: not used
8-9 L2CPC
10
Pin mux: BADDR
10-11 DPPC 00 Pin mux: IRQ
12 Reserved 0 ---
13-15 ISB 111 Internal space address start: $FFF0 0000
16 BMS 1 BR0[BA] for boot: $0000 0000
17 BBD 0 Pin mux: DBB
18-19 MMR 00 All external bus master: not used
20-21 LBPC 00 Local bus pins as: local bus
22-23 APPC
10
Pin mux: BNKSEL
24-25 CS10PC 00 Pin mux: CS10
26 Reserved 0 ---
27 Reserved 0 ---
28-31 MODCK_H
0101
Clock configuration: bus 66, CPM 133, core 133 or 200
Then the Reset Word mapping in Flash memory is :
Byte 0, address $0000 = $0E
Byte 1, address $0008 = $87
Byte 2, address $0010 = $82
Byte 3, address $0018 = $05

If the two banks contains an invalid ResetWord, the ResetConf jumper (J2) can
force the PowerQUICC II to uses his default ResetWord.
The ResetWord is then programmed through the JTAG port.

Some JTAG tools may need the CheckStop signal on the JTAG connector.
In this case, due to the 8260 pin multiplexing, the ResetWord must be modified
with DPPC = 10 while using the JTAG tool.
For normal board use, keep the value 00.
Warning
The MODCK_H bits must be set to the described value.
If other values are set, the internal speeds can be higher than expected by the
processor, and then it will heat more than acceptable thus can be destroyed.
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