Specifications

Rev. 1.43
User's Guide
83
The VSBC-6862 uses these reset signals with an equivalent circuitry than following:
Figure 21: Reset scheme
The PORESET can be generated by:
- the VSBC-6862's power monitor (MAX700)
- the RTC's watchdog, depending of the SRESR register settings
- the push-button on front panel
- an external jumper
- a specific write operation in register of programmable logic
and is sent to:
- the PowerQUICC II
- the programmable logic
- the VME bus when board in not in slot 1 and specific jumper is installed
The HRESET can be generated by:
- a specific write operation in register of programmable logic
- the P3 connector
and is sent to:
- the PowerQUICC II
- all board's devices excepted the programmable logic and Flash devices
- the VME bus when board is in slot 1 and specific jumped is installed
The SRESET can be generated by:
- a specific write operation in register of programmable logic
- the P3 connector
and is sent to:
- the PowerQUICC II
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The Flash memory is connected to his own Reset line commanded by the
SRESR register. This memory is not connected to any other Reset signal.
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