Specifications

Rev. 1.43
User's Guide
73
PHY register address 4: Auto-Negotiation Advertisement Register
Bit NAME DESCRIPTION R/W DEFAULT
15 Next Page 1 = additional link code word pages
0 = no additional pages
RO 0
14 Acknowledge 1 = received ANeg Word recognized
0 = not recognized
RO 0
13 Remote fault 1 = ANeg remote fault detected
0 = no remote fault detected
R/W 0
12:10 Reserved Reserved R/W 0
9 T4 1 = capable of 100Base-T4
0 = not capable
R/W 0
8 TX_FDX 1 = capable of 100Base-TX Full-Duplex
0 = not capable
R/W 1
7 TX_HDX 1 = capable of 100Base-TX Half-Duplex
0 = not capable
R/W 1
6 10_FDX 1 = capable of 10Base-T Full-Duplex
0 = not capable
R/W 1
5 10_HDX 1 = capable of 10Base-T Half-Duplex
0 = not capable
R/W 1
4:1 Reserved Reserved RO 0
0 CSMA 802.3 capable 1 = capable of 802.3 CSMA operation
0 = not capable
RO 1
PHY register address 17: Structure and Bit definition
Bit NAME DESCRIPTION R/W DEFAULT
15, 14 Programmable LED output 3 11 = normal
10 = LED blink
01 = LED on
00 = LED off
R/W 11
13,12 Programmable LED output 2 11 = normal
10 = LED blink
01 = LED on
00 = LED off
R/W 11
11, 10 Programmable LED output 1 11 = normal
10 = LED blink
01 = LED on
00 = LED off
R/W 11
9,8 Programmable LED output 0 11 = normal
10 = LED blink
01 = LED on
00 = LED off
R/W 11
7,6 LED function See table 'LED function' below R/W 00
5 Auto-polarity disable 1 = MII interface disabled
0 = normal operation
R/W 0
4 Jabber disable 1 = restart auto negotiation
0 = normal
R/W 0
3 Multiple register access 1 = Full duplex mode
0 = Half duplex mode
R/W 0
2 Interrupt scheme 1 = enable COL signal test
0 = normal
R/W 0
1 R/J configuration 1 = RX_EN/nJAM pin is nJAM
0 = RX_EN/nJAM pin is RX_EN
R/W 0
0 Reserved Reserved, must be 0 R/W 0
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