Specifications
Rev. 1.43
User's Guide
69
4.9. Fast Ethernet ports
4.9.1. Transceivers description
The two fast Ethernet interfaces come directly from the MPC-8260 processor. The physical layer is
achieved with on-board fast Ethernet transceivers.
The SMSC-LAN83C183 provides all of the IEEE 802.3u 100Base-TX and ISO802.3 10Base-T
Physical Layer (PHY) functions needed for workstations, bridge, router, and switch applications. It can
operate as a 100Mbps only device, or as a dual speed 10/100Mbps device with built-in auto-
negotiation possibility for speed selection. The SMSC-LAN83C183 supports the standard Media
Independent Interface (MII) for glueless interface with 10/100 Ethernet Media Access Controllers
(MAC).
The built-in IEEE 802.3u Auto-Negotiation feature automatically selects internal 10Base-T or
100Base-TX, full or half-duplex, as a result of negotiation between the station and its link partner.
The SMSC-LAN83C183 supports half and full-duplex operation at both 10Mbps and 100Mbps speeds.
It complies with ANSI X3T9 TP-PMD and includes MLT-3 Encoder/Decoder and Stream Cipher
scrambler/ de-scrambler functions for 100Base-TX.The SMSC-LAN83C183 supports Category 5
Unshielded Twisted Pair and Type 1 Shielded Twisted Pair wiring. The on-chip Serial Management
Interface features the Basic and Extended registers set. The 4B/5B Encoder and Decoder are also
included.
An on-board transformer provides a direct connection for a 10Base-T and 100Base-TX interface
Specific hardware configuration as defined by the VSBC-6862 is like the following:
Fast Ethernet Port 1
PHY address: $1
Speed select: 100 Mbps
Auto-negotiation: enabled
Duplex: full
Fast Ethernet Port 2
PHY address: $1
Speed select: 100 Mbps
Auto-negotiation: enabled
Duplex: full
Note that these default values (expected PHY address) can be changed at any time through the serial
management interface.
It's to be noted that the two Fast Ethernet PHY have the same address. Each transceiver is connected
on an independent MII channel.
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