Specifications
Rev. 1.43
User's Guide
63
Typical Option Register:
Bit Field Value Function
0-16 AM $FC00 0 Address mask: for 64 MBytes
17-18 Reserved 00 ---
19 BCTLD 0 Buffer control: on
20-22 Reserved 000 ---
23 Burst inhibit 1 Burst disabled
24-28 Reserved 00000 ---
29-30 EHTR 01 One idle clock inserted
31 Reserved 0 ---
-> OR6-7 = $FC00 0102
The UPM C must also be defined. The definition is the same as for the UPM A and UPM B described
in the IP modules chapter.
The two VME windows have the same VME request level.
(see the VMBA register description)
For the VME master, the release mode is selectable between ROR and RWD modes with the VMBA
register.
- ROR mode: Release On Request, the VSBC-6862 keeps the bus until an VME Bus Clear
signal is coming. This mode permits the VSBC-6868 to access the VME bus
without having to request the bus, thus, accelerates the bus access.
- RWD mode: Release When Done, the VSBC-6866 releases the VME bus after each
access.
The VME Master also includes a 'pseudo-RMW' cycle to facilitate the usage of sharable memory.
It is called 'pseudo-RMW' cycle because it does not comply with the VME standard 'RMW' definition,
but it can achieve the same result. This function is available through the VSBA24[VME_RMW] bit.
In fact, when the 'pseudo-RMW' cycle is active, the VME Master do not release the BBSY and AS
signals. This permits to keep the bus to our exclusive usage.
The normal usage of this function is as:
- Activation of the 'pseudo-RMW' cycle function
- Make VME master cycles, please limit the number of these cycles to a minimum amount
- Deactivation of the 'pseudo-RMW' cycle function
Warning
The 'pseudo-RMW' cycle is not time-limited. If the bus as not been released
between either the VME bus timeout, either the local slave's timeout, it will
create respectively either VME bus errors for the other VME masters, either
local bus error on the slave. Thus please use the minimum VME cycles
between the activation and the deactivation of this function.
If a VME bus error occurs on a 'pseudo-RMW' cycle, the VME bus is released and
the 'pseudo-RMW' cycle is also deactivated to avoid bus lockout.
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