Specifications
VSBC-6862 Rev 1.43
56
Typical Option Register:
Bit Field Value Function
0-16 AM $FE00 0 Address mask: for 32 MBytes
17-18 Reserved 00 ---
19 BCTLD 0 Buffer control: on
20-22 Reserved 000 ---
23 Burst inhibit 1 Burst disabled
24-28 Reserved 00000 ---
29-30 EHTR 00 No idle clock inserted
31 Reserved 0 ---
-> OR5 = $FE00 0100
Both UPM A and UPM B must be loaded with the following values:
UPM's RAM address Value
Single Read Access
0x0
0x00fcec00
0x1
0x00fcfc40
0x2
0x00fcfc40
0x3
0x11fdec05
Single Write Access
0x18
0x00fccc00
0x19
0x00fcfc40
0x1A
0x00fcfc40
0x1B
0x11fdec05
Exception cycle
0x3C
0xffffcc01
These values define the needed patterns for the memory controller signals.
The Wait Mechanism is defined in this definition to accomodate the unprevisible acknowledge time for
the VME and IP cycles.
This UPM Ram must be loaded as described in the MPC8260 Reference Manual, Memory Controller
chapter. This will be resumed as:
Description Example
Set the Base Register
*BR4=0xfa001081
Set the Option Register
*OR4=0xffff8100
Set the MxMR to write at offset 0 for Single Read
*MAMR=0x10040000
Set the MDR with the value to write
*MDR=0x00fcec00
Make an access in the corresponding Chip Select space (write UPM RAM)
*CS4=0
Set the MDR with the next value (the MxMR is auto-incremented)
*MDR=0x00fcfc40
Access the CSx memory space
*CS4=0
(Continue for all Single Read UPM Words)
...
Set the MxMR to write at offset 18 for Single Write
*MAMR=0x10040018
Set the MDR with the value to write
*MDR=0x00fccc00
Make an access in the corresponding UPM space to load the UPM RAM
*CS4=0
Set the MDR with the next value (the MxMR is auto-incremented)
*MDR=0x00fcfc40
Access the CSx memory space
*CS4=0
(Continue for all Single Write UPM Words)
...
Set the MxMR to write at offset 3C for Exception cycle
*MAMR=0x1004003C
Set the MDR with the value
*MDR=0xffffcc01
Access the CSx memory space
*CS4=0
Set the MxMR in normal mode
*MAMR=0x00040000
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