Specifications

Rev. 1.43
User's Guide
55
The IP interface uses two processor chip selects to cover all IP module spaces.
The I/O, ID, and INT spaces are controlled by the Chip Select 4.
The memory space is controlled by the Chip Select 5.
Chip Select 4 configuration
Typical Base Register:
Bit Field Value Function
0-16 BA $xxxxb Base address: user defined
17-18 Reserved 00 ---
19-20 PS 10 Port size: 16 bits
21-22 DECC 00 Data error correction: off
23 WP 0 Write protect: off
24-26 MS 100 Machine select: UPM A
27 EMEMC 0 External mem cntrl enable: off
28-29 ATOM 00 Atomic operation: off
30 DR 0 Data pipelining: no
31 V 1 Valid bit: on
-> BR4 = $xxxx 1081
Typical Option Register:
Bit Field Value Function
0-16 AM $FFFF 1 Address mask: for 32 kBytes
17-18 Reserved 00 ---
19 BCTLD 0 Buffer control: on
20-22 Reserved 000 ---
23 Burst inhibit 1 Burst disabled
24-28 Reserved 00000 ---
29-30 EHTR 00 No idle clock inserted
31 Reserved 0 ---
-> OR4 = $FFFF 8100
Chip Select 5 configuration
Typical Base Register:
Bit Field Value Function
0-16 BA $xxxxb Base address: user defined
17-18 Reserved 00 ---
19-20 PS 10 Port size: 16 bits
21-22 DECC 00 Data error correction: off
23 WP 0 Write protect: off
24-26 MS 101 Machine select: UPM B
27 EMEMC 0 External mem cntrl enable: off
28-29 ATOM 00 Atomic operation: off
30 DR 0 Data pipelining: no
31 V 1 Valid bit: on
-> BR5 = $xxxx 10A1
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