Specifications

VSBC-6862 Rev 1.43

48T37V partial register map is:

Base + D7 D6 D5 D4 D3 D2 D1 D0 Function (Range) BCD format

$7FFF 10 Years Year Year (00-99)

$7FFE 0 0 0 10M. Month Month (01-12)

$7FFD 0 0 10 Date Date Date (01-31)

$7FFC 0 FT 0 0 0 Day Century/Day (0-1/01-07)

$7FFB 0 0 10 Hours Hours Hour (00-23)

$7FFA 0 10 Minutes Minutes Minutes (00-59)

$7FF9 ST 10 Seconds Seconds Seconds (00-59)

$7FF8 W R S Calibration Control

$7FF7 WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog

$7FF6 AFE 0 ABE 0 0 0 0 0 Interrupts

$7FF5 RPT4 0 Alarm 10 Date Alarm Date Alarm Date (01-31)

$7FF4 RPT3 0 Alarm 10 Hours Alarm Hours Alarm Hours (00-23)

$7FF3 RPT2 Alarm 10 Minutes Alarm Minutes Alarm Minutes (00-59)

$7FF2 RPT1 Alarm 10 Second Alarm Seconds Alarm Seconds (00-59)

$7FF1 1000 Years 100 Years Century

$7FF0 WDF AF Z BL Z Z Z Z Flags

With: S = sign bit AF = Alarm Flag

FT = Frequency Test bit BL = Battery Low Flag

R = Read Bit WDS = Watchdog Steering Bit

W = Write Bit BMB0-BMB4 = Watchdog Multiplier Bits

ST = Stop Bit RB0-RB1 = Watchdog Resolution Bits

0 = Must be set to ’0’ AFE = Alarm Flag Enable

Z = ’0’ and are Read only ABE = Alarm in Battery Back-up Mode Enable

WDS = Watchdog Steering Bit RPT1-RPT4 = Alarm Repeat Mode Bits

WDF = Watchdog Flag

4.5.1. RTC registers read operation

The RTC registers are continuously updated by the device.

Updates to the RTC registers should be halted before clock data is read to prevent reading data in

transition.

Because the registers are only copy of the clock counters, updating the registers can be halted without

disturbing the clock itself. Updating is halted when a ’1’ is written to the READ bit, D6 in the Control

registers reflect the count; that is, the day, date, and the time that was current at the moment the halt

command was issued. All of the RTC registers are updated simultaneously. A halt will not interrupt an

update in progress. Updating is within a second after the bit is reset to a ’0’.

4.5.2. RTC registers write operation

Bit D7 of the Control Register 7FF8h is the WRITE bit. Setting the WRITE bit to a ’1’, like the READ

bit, halts updates to the RTC registers. The user can then load them with the correct day, date, and

time data in 24 hour BCD format. Resetting the WRITE bit to a ’0’ then transfers the values of all time

registers 7FF9h-7FFFh to the actual RTC counters and allows normal operation to resume. After the

WRITE bit is reset, the next clock update will occur in approximately one second.



See the ST Microelectronics Application Note AN923 "TIMEKEEPER rolling into

the 21st century" on the ST Web site for information on Century Rollover.

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