Specifications

Rev. 1.43
User's Guide
51
4.5. Real Time Clock with SRAM memory
The VSBC-6862 includes a real time clock device, with as an additional feature, a battery backed
32 kByte SRAM.
This 32 kByte SRAM provides a flexible user data storage with retention capability by its SNAPHAT
battery pack. This device is connected on an 8 bits wide data path.
This device provides also functions like Alarm, Battery Test, and Watchdog function.
The GPCM is used to control the Real Time Clock and the battery backed SRAM.
The RTC data are mapped in the SRAM memory map.
The RTC is also accessible from VME bus.
Typical Base Register:
Bit Field Value Function
0-16 BA $xxxxb Base address: user defined
17-18 Reserved 00 ---
19-20 PS 01 Port size: 8 bits
21-22 DECC 00 Data error correction: off
23 WP 0 Write protect: off
24-26 MS 000 Machine select: GPCM on 60x bus
27 EMEMC 0 External mem cntrl enable: off
28-29 ATOM 00 Atomic operation: off
30 DR 0 Data pipelining: no
31 V 1 Valid bit: on
-> BR3 = $xxxx 0801
Typical Option Register:
Bit Field Value Function
0-16 AM $FFFF 1 Address mask: for 32 kBytes
17-18 Reserved 00 ---
19 BCTLD 0 Buffer control: on
20 CSNT 0 Chip select negation time: normal
21-22 ACS 00 Address to CS setup: 0
23 Reserved 0 ---
24-27 SCY 0111 Cycle length: 7
28 SETA 1 External access termination: external
29 TRLX 0 Timing relaxed: off
30 EHTR 0 Extended hold time: off
31 Reserved 0 ---
-> OR3 = $FFFF 8078
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