Specifications

VSBC-6862 Rev 1.43
50
4.4. SRAM memory
The VSBC-6862 includes 1 MByte SRAM for fast exchanges with external VME masters.
With its backup capability with the VME Stand-By power line, this memory can be also useful to
backup critical data.
This memory is handled with the GPCM through the Chip Select 9.
It is organized with two 16 bits wide chips to achieve a data width of 32 bits.
Typical Base Register:
Bit Field Value Function
0-16 BA $xxxxb Base address: user defined
17-18 Reserved 00 ---
19-20 PS 11 Port size: 32 bits
21-22 DECC 00 Data error correction: off
23 WP 0 Write protect: off
24-26 MS 000 Machine select: GPCM on 60x bus
27 EMEMC 0 External mem cntrl enable: off
28-29 ATOM 00 Atomic operation: off
30 DR 0 Data pipelining: no
31 V 1 Valid bit: on
-> BR9 = $xxxx 1801
Typical Option Register:
Bit Field Value Function
0-16 AM $FFF0 0 Address mask: for 1 MBytes
17-18 Reserved 00 ---
19 BCTLD 0 Buffer control: on
20 CSNT 0 Chip select negation time: normal
21-22 ACS 00 Address to CS setup: 0
23 Reserved 0 ---
24-27 SCY 0110 Cycle length: 6
28 SETA 1 External access termination: external
29 TRLX 0 Timing relaxed: off
30 EHTR 0 Extended hold time: off
31 Reserved 0 ---
-> OR9 = $FFF0 0068
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com