Specifications

VSBC-6862 Rev 1.43
48
4.3. SDRAM memory
This memory is handled by the powerful SDRAM timing machine contained in the MPC-8260.
The SDRAM machine provides an interface to synchronous DRAMs, using SDRAM pipelining, bank
interleaving, and back-to-back page mode to achieve the highest performance. This controller
supports directly all the SDRAM possibilities, like pipelining and interleaving.
The VSBC-6862 is supplied with 128 MBytes SDRAM on-board, organized with four 16Mbitsx16
devices.
The 64 bits wide data bus is directly connected on the 60x bus of the MPC-8260 to achieve the best
performance.
The SDRAM is controlled by the Chip Select 1 signal.
4.3.1. SDRAM initialization
This device have specific operation for initialization, both SDRAM machine and SDRAM devices have
to be set-up.
The SDRAM machine is configured with its own set of registers as OR1, BR1, PSDMR.
The SDRAM device is configured by accessing the PSDMR register in a specific manner.
Here follows the full description to initialize the SDRAM devices:
- Configure MPTPR: timer prescaler
- Configure PSRT: refresh timer prescaler
- Configure OR1
- Configure BR1
- With PSDMR, issue a PRECHARGE-ALL-BANKS command
- " issue eight CBR REFRESH commands
- " issue a MODE-SET command to initialize the mode register with the
below recommended value
- The SDRAM can now be used as normal memory
With:
Typical Base Register:
Bit Field Value Function
0-16 BA $xxxxb Base address: user defined
17-18 Reserved 00 ---
19-20 PS 00 Port size: 64 bits
21-22 DECC 00 Data error correction: off
23 WP 0 Write protect: off
24-26 MS 010 Machine select: SDRAM on 60x bus
27 EMEMC 0 External mem cntrl enable: off
28-29 ATOM 00 Atomic operation: off
30 DR 0 Data pipelining: no
31 V 1 Valid bit: on
-> BR1 = $xxxx 0041
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