Specifications

VSBC-6862 Rev 1.43
44
4.2. FLASH memory
Two banks of Flash devices are available.
Each bank is 4 or 8 MBytes wide for a total of 8 or 16 MBytes Flash.
The GPCM is used to control the Flash memory.
Each bank is controlled by the Chip Select 0 (CS0) or Chip Select 2 (CS2) signal.
The Flash memory has boot capability in accordance with the 'Bootbank' jumper setting.
The granularity is 16 bits, it means that the minimum size accessible in the Flash memory is two bytes.
This device is command set compatible with JEDEC standard E
2
PROMs.
Commands are written to the command register using standard microprocessor write timings. Register
contents serve as input to an internal state-machine which controls the erase and programming
circuitry.
This Chip Select (CS0) is the Boot Chip Select, it is connected to a Flash memory bank.
When the power goes to ON, the Flash memory bank connected to this chip select must contain the
Reset initialization Word for the PowerQUICC II, and is boot code. If the Reset Word is not valid, the
board can be started with a default Reset initialization Word using the 'Resetconf' jumper on J2.
For more convenience, we have added the possibility to switch the Flash memory bank 0 and the
bank 1 between CS0 and CS2, thus inverting the bootable bank.
This is done by manipulating the 'BootBank1' jumper.
The bootable Flash memory bank is also accessible from the VME bus. See the VME slave chapter
for more information.
4.2.1. FLASH initialization
Typical Base Register:
Bit Field Value Function
0-16 BA $xxxxb Base address: user defined
17-18 Reserved 00 ---
19-20 PS 11 Port size: 32 bits
21-22 DECC 00 Data error correction: off
23 WP 0 Write protect: off
24-26 MS 000 Machine select: GPCM on 60x bus
27 EMEMC 0 External mem cntrl enable: off
28-29 ATOM 00 Atomic operation: off
30 DR 0 Data pipelining: no
31 V 1 Valid bit: on
-> BR0 = $xxxx 1801
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