Specifications

VSBC-6862 Rev 1.43
112
Performance issues
The VSBC-6862 has been designed for providing efficient performance with peripheral connected
around the PowerQUICC II processor.
The following table provides the respective wait states that should be expected for each access type.
Conditions: MPC-8260 @ 200 MHz
Access Number of cycles
FLASH
Read cycle single beat TBD
SDRAM
Read cycle single beat TBD
Write cycle single beat TBD
Read cycle burst (4 transfers) TBD
Write cycle burst (4 transfers) TBD
IP module, 8 MHz mode, memory space
Read cycle single beat TBD
Write cycle single beat TBD
IP module, 8 MHz mode, other spaces
Read cycle single beat TBD
Write cycle single beat TBD
Board registers
Read cycle single beat TBD
Write cycle single beat TBD
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