Specifications
VSBC-6862 Rev 1.43
108
VIVEC VME Interrupter Vector RW
CS4 + $106d
VME slave + 7
This register contains IRQ level and the vector sent by the VME interrupter.
8260 D8 D9 D10 D11 D12 D13 D14 D15
VME D7 D6 D5 D4 D3 D2 D1 D0
Value
IL2 IL1 IL0 Vec4 Vec3 Vec2 Vec1 Vec0
Default
0 0 0 0 0 0 0 0
With: IL2-IL0: IRQ level coded on 3 bits. IRQ level = 0 implies that no IRQ will be
sent when writing the VINTER register
Vec4-Vec0: Low order bits of the vector sent by the interrupter during interrupt-
acknowledge cycle. High order bits are IRQ level acknowledged
coded on 3 bits.
Warning
This register is accessible from both VME bus and local processor.
The user must choose that this register is accessed by either VME either local
processor, but never both at the same time.
VSMAIL VME Slave Mailbox WO
CS4 + $1065
VME slave + 1
This register implements a single mailbox.
8260 D8 D9 D10 D11 D12 D13 D14 D15
VME D7 D6 D5 D4 D3 D2 D1 D0
Value
x x x x x x x x
Default
x x x x x x x x
When an external VME master writes any value in this register, and the VSBA24[MailOn] bit is set, an
IRQ6 is sent to the MPC-8260.
To clear this interrupt, the MPC-8260 must write any value to this register.
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