Specifications

Rev. 1.43
User's Guide
107
VHV VME Interrupter Vector RO
CS4 + $1073 to CS4 + $107f
When accessed, this register acknowledges the corresponding VME interrupt as:
VME IRQ to acknowledge VHV address
1 CS4 + $1072
2 CS4 + $1074
3 CS4 + $1076
4 CS4 + $1078
5 CS4 + $107a
6 CS4 + $107c
7 CS4 + $107e
Value:
D8 D9 D10 D11 D12 D13 D14 D15
Value
V7 V6 V5 V4 V3 V2 V1 V0
Default
x x x x x x x x
With: V0-V7: Vector

Reading this register initiates a Interrupt Acknowledge cycle only if
corresponding interrupt is not masked.
Reading this register when no IRQ is pending, is not allowed
VINTER VME Interrupter command register WO
CS4 + $1067
This register generates the corresponding VME IRQ.
8260 D8 D9 D10 D11 D12 D13 D14 D15
Value
x x x x x x x x
Default
x x x x x x x x
Writing any value to this register will generate an IRQ to the VME bus.
The IRQ level is defined by the VIVEC[ILx] bits described above in this chapter.
The IRQ is automatically cleared when the interrupt acknowledge cycle is completed.
For debug purposes, the SRESR register can be used to manually clear this interrupt.
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