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USER'S GUIDE VSBC-6862 VME Single Board Computer with PowerQUICC II processor Revision 1.43 3105 ACTIS Computer www.actis-computer.com support@actis-computer.com Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.
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Rev. 1.43 User's Guide Table of contents 1 1.1. 1.2. 1.3. 1.4. 1.5. 2 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 2.7. 2.8. 2.9. 2.10. 2.11. 2.12. 2.13. 3 3.1. 3.2. 3.3. 3.4. 3.5. 3.6. 3.7. 3.8. 3.9. 3.10. 3.11. 3.12. 3.13. 3.14. 3.15. 3.16. 3.17.
VSBC-6862 Rev 1.43 4.2.5. FLASH sector protection: option on request_________________________________ 4.3. SDRAM memory ________________________________________________________ 4.3.1. SDRAM initialization ___________________________________________________ 4.4. SRAM memory _________________________________________________________ 4.5. Real Time Clock with SRAM memory ________________________________________ 4.5.1. RTC registers read operation ____________________________________________ 4.5.2.
Rev. 1.43 User's Guide 7 8 9 Registers definition ________________________________________________________ 99 Characteristics __________________________________________________________ 111 Physical board definition ___________________________________________________ 113 9.1. 9.2.
VSBC-6862 Rev 1.43 List of figures Figure 1: Photograph............................................................................................................................... 9 Figure 2: Block diagram......................................................................................................................... 10 Figure 3: Component location ...............................................................................................................
Rev. 1.43 User's Guide 1 Product description 1.1. Introduction Today industrial applications are growing in telecom market due to the demand of networked architecture. This method offers great advantage where complex processes are handled and where real time tasks are the critical features. The VSBC-6862 combines the best possibilities with its flexible industrial interface and its wide range of communications ports.
VSBC-6862 Rev 1.43 1.2. Features This board has been designed to integrate the most required functions, including several Fast Ethernet ports, communication ports, and the flexibility of four IP modules slots for easy user's customization. • Designed with Motorola PowerQUICC II processor • A 32-bit EC603 ™ processor core rated at 280.0 MIPS at 200 MHz (Dhrystone 2.
Rev. 1.43 User's Guide 1.3. Photograph Figure 1: Photograph The VMEbus Technology logo is a Trademark of the VMEbus International Trade Association. 9 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.
VSBC-6862 Rev 1.43 1.4. Block diagram The VSBC-6862 architecture is divided in four main sections: The CPU This is the heart of the board, it is the MPC-8260 'PowerQUICC II' with a bus speed of 66MHz, CPM speed of 133MHz and Core speed of 133 or 200MHz. The memory section This section includes the 128 MByte SDRAM on a 64-bit bus, the two 8 MByte Flash memory banks on a 32-bit bus, the 1 MByte SRAM memory, and the battery backed-up RTC with SRAM.
Rev. 1.43 User's Guide 1.5. Component location Figure 3: Component location 11 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.
VSBC-6862 Rev 1.43 Please note that on the VSBC-6862, some locations are not populated. This was done either to avoid problems of component availability, either for debug purposes. From the user side, its totally transparent, nothing has to be modified. For special uses that need a precise component implementation, please contact ACTIS. 12 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.
Rev. 1.43 User's Guide 2 Peripherals description The VSBC-6862 offers a wide choice of on-board peripheral or bus interface, which makes this board very versatile. Most of these peripherals comes either directly from the processor interface, like the serial ports, or from other interface unit, like the real time clock calendar. The following sections will describe these peripheral features. 2.1.
VSBC-6862 Rev 1.43 2.3. SRAM memory 1 MBytes of SRAM memory are provided on-board, this memory is controlled with the Chip Select 9. This memory is shared between the PowerQUICC II and the VME bus. It is organized in memory width of 32 bits. A special function is provided for memory saving with the usage of the Stand-By power signal from the VME bus. When the Board Power is shutdown, the SRAM memory will switch its power lines to the VME Stand-By power signal. 2.4.
Rev. 1.43 User's Guide The IP interface uses two processor chip selects to address all IP module spaces. The Chip Select 4 is used to control the IP I/O, ID, and INT spaces. The Chip Select 5 is used to control the IP memory spaces. Each IP slot has is own set of registers to have the four IP slots fully independent. The VSBC-6862 supports the two IRQ available on the IP modules. Each IP slot has an own IRQ level attributed to the MPC-8260.
VSBC-6862 Rev 1.43 The VME interrupter I(1-7) The interrupter is able to generate any VME IRQ level and send a user-defined vector. The VME interrupt-handler IH(1-7) This interrupt-handler is able to recognize all IRQ VME levels. All levels can be masked with the VHM register. When an IRQ is coming from the VME side, an IRQ1 is sent to the MPC-8260. The user can then read the IRQ levels active in the VHIL register.
Rev. 1.43 User's Guide 2.8. I2C EEPROM 8 kbits of non-volatile memory is provided on the I2C bus. This memory is used for board internal configuration (for example to store physical Fast Ethernet addresses) and can also be used for user purposes. 2.9. Fast Ethernet ports The two Fast Ethernet interfaces come directly from the MPC-8260 processor. The physical layer is achieved with on-board fast Ethernet transceivers from SMSC: the LAN83C183. The SMSC-LAN83C183 provides all of the IEEE 802.
VSBC-6862 Rev 1.43 2.11.SCC multi-protocols serial ports The VSBC-6862 offers four independent serial ports. In synchronous mode, all four ports have independents RX clock signals, but only SCC1 and SCC2 have TX Clocks signals. These ports are directly controlled by the Serial Communication Controllers (SCC) included in the PowerQUICC II. These SCC includes functions like support of many protocols like UART and HDLC, it contains also FIFO buffers: 32 byte deep, and many more powerful options.
Rev. 1.43 User's Guide 2.12.I2C interface The VSBC-6862 provides an I2C interface bus for on-board serial EEPROM accesses and user purposes. The board provides external accesses to this bus through an internal connector. 2.13.LED displays The VSBC-6862 allows monitoring for a wide range of board activities, these status are available for user check on the front panel. The Power and Access LEDs functions are hardware fixed.
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Rev. 1.43 User's Guide 3 Connectors & jumpers This chapter will describe all connectors and jumpers on the VSBC-6862. One of specificity of this board is that the four IP slots occupy most of the board's surface. And it is not possible to locate connector or jumpers on this area. In spite of this fact, ACTIS placed the connectors and jumpers in a very straightforward location.
VSBC-6862 Rev 1.43 Locations Figure 4: Connectors and jumpers location 22 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.
Rev. 1.43 User's Guide 3.1. Push Button: BP1 In the front panel, the push button generates a Power-On Reset to the board. This button is debounced. Figure 5: Push button location Before SN:10135, the Push Button was generating a Hardware Reset instead of Power-On Reset. 3.2. Rotary switch: SW1 The eight position rotary switch is a facility provided for user purposes. This switch can be used, for example, to select the board working modes. It can be read with the SWPR register.
VSBC-6862 Rev 1.43 3.3. IP module strobes, header J1 For IP module operations, an optional "STROBE" signal is provided for each IP module sockets. This signal is provided for general purpose use, the J1 header allows the selection for both signals with the following assignment. The VSBC-6862 has internals pull-ups connected to these Strobe signals. Jumpers permit to access or connect pull-downs to these signals.
Rev. 1.43 User's Guide 3.4. Jumper: J2 A jumper with six positions provides some basic functions. Figure 8: Jumper J2 location Position 1 Description: BootBank1 Description Unplugged Plugged-in The board boots on the Flash memory bank 0 The board boots on the Flash memory bank 1 This jumper is used to define which Flash memory bank is the boot bank. The VSBC-6862 as two Flash memory banks. The usage of this jumper allows the user to reverse the bootable bank.
VSBC-6862 Rev 1.43 Position 4 Description: VME Reset Out Factory seting Description Unplugged Plugged-in X Board is not authorized to generate a VME Reset Board in Slot1 mode is authorized to generate a VME Reset When this jumper is plugged, if the board is in Slot1 mode, it will generate a VME Reset when the board is under Hardware Reset.
Rev. 1.43 User's Guide 3.6. Jumpers: J4, J5, J6, J7 This are the 'serial mode' jumpers, they have six position. They permits to select the mode used for the corresponding serial port. All the six positions of these jumpers must be either all in RS-232 position, either all in RS-485 position.
VSBC-6862 Rev 1.43 3.7. Jumper: J8 This jumper sets the base address for the A16 slave window. This window contains all registers accessible from an external VME master. A jumper plugged represents an address line in the state '0', with: position 1: position 2: position 3: position 4: position 5: VME address A11 VME address A12 VME address A13 VME address A14 VME address A15 Example: Figure 12: Jumper J8 location This configuration indicates a A16 window base address of $F800.
Rev. 1.43 User's Guide 3.8. Two RS-232 terminal ports, and I2C bus: P13, P4 These serial ports are provided for general purpose application, its interface levels comply with the RS-232 specification. In most environments, these interfaces will be used as a console port for board configuration and monitoring functions. These ports are handled by the SMC1 and SMC2 functions of the PowerQUICC II processor.
VSBC-6862 Rev 1.43 The second serial port is available in an internal connector shared with the I2C bus. P4 contains the signals for the SMC2, power lines for user purposes (max 500mA, fused), and the I2C bus extension. This connector is available on-board through a HE-10 connector defined as following: 2 4 6 8 10 1 3 5 7 9 Figure 14: Connector P4 pinout Pin 1 2 3 4 5 6 7 8 9 10 Signal n.u. 3.3V 5V n.u. GND GND I2CSCL I2CSDA TXD2 RXD2 Description Not used 3.3 V, 500mA fuse 5.
Rev. 1.43 User's Guide 3.9. Four multi-protocols serial ports P7,P8,P9, P10 These four serial ports are provided for user applications These four ports are available in the front panel on four HD-15 connectors with: Port SCC1: connector P7 Port SCC2: connector P8 Port SCC3: connector P9 Port SCC4: connector P10 All signals on these connectors are in full-duplex mode. For Half-duplex mode, please connect externally RX and TX.
VSBC-6862 Rev 1.43 Termination network resistors When the RS-422/RS-485/V.35 is chosen, the VSBC-6862 is provided with removable network resistors. Each resistor network is located as: RZ34, RZ35: RZ36, RZ37: RZ38, RZ39: RZ40, RZ41: port SCC 1 port SCC 2 port SCC 3 port SCC 4 Note that the pins 1 of these removable networks are in opposed side than the already soldered resistor network. Figure 16: Termination resistor networks example 32 Artisan Technology Group - Quality Instrumentation ...
Rev. 1.43 User's Guide 3.10.Two Fast Ethernet ports, connectors P11, P12 For LAN based applications, two fast Ethernet connections are available for twisted-pair interface which is compliant for both 100Base-TX and 10Base-T specification described below. The PHY part of the BSBC-6862 is based on the SMSC83C183 transceiver. Front panel, connector Fast Ethernet 1 = connector P12, corresponds to FCC2. Front panel, connector Fast Ethernet 2 = connector P11, corresponds to FCC1.
VSBC-6862 Rev 1.43 3.11.IEEE-1149.1 interface, connector P3 The MPC-8260 provides a dedicated user-accessible test access port (TAP) that is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems associated with testing high-density circuit boards have led to development of this standard under the sponsorship of the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG).
Rev. 1.43 User's Guide 3.12.
VSBC-6862 Rev 1.43 3.13.
Rev. 1.43 User's Guide Signal +5 V +12 V -12 V GND +5 V STDBY TM 5 V Description Main power supply Power used for IP module slots and Flash protection feature Power used for IP module slots Ground Power supply furnished by an non-interruptible power source 5 V provided by the VSBC-6862 to an optional transition module. Fuse protected This connector is compliant with the DIN-41612 specification. 37 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.
VSBC-6862 Rev 1.43 3.14.Four IP module logic interface, connectors P3A, P4A, P5A, P6A For input/output extensions, the VSBC-6862 board provides a four slot IP module interface. This bus interface complies with the ANSI/VITA-4 1995 specification and handles 16-bit wide modules and supports 8 MHz mode.
Rev. 1.43 User's Guide 3.15.Four IP module I/O signals, connectors P3C, P4C, P5C, P6C The four IP modules slots present on the VSBC-6862 have their I/O connections available on four high density connectors. They are connectors from Hirose (Ref: HIF6A-50PA-1,27DSA). The corresponding Hirose cable connector reference is: HIF6-50D-1,27R.
VSBC-6862 Rev 1.43 3.16. Real time clock battery, circuit U5 The VSBC-6862 provides a real time clock for calendar function. This device includes also a 32 kByte SRAM with battery backed capability. It also include an on-chip watchdog that can be used as board's Watchdog. The battery used by this part is a Lithium type and is designed for user replacement.
Rev. 1.43 User's Guide 3.17. Fuses protection The VSBC-6862 offers a flexible I/O extension facility through its quad IP module interface. Therefore some cautions must be taken to avoid hardware damage in case of short circuit. This function is handled by a set of on-board fuses. These fuses are thermal controlled, when a short-circuit arise, the fuse will automatically break the circuit. When it will be cold, it becomes again normal.
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Rev. 1.43 User's Guide 4 Software description 4.1. Introduction The PowerQUICC II includes a very versatile and powerful memory controller. This controller permits to define by software the base memory for each chip select, thus to define the memory map. The memory controller is composed of three internal machines: - The general purpose chip select machine: GPCM provides signal generation for local resources: SRAM and FLASH memory, and Real Time Clock.
VSBC-6862 Rev 1.43 4.2. FLASH memory Two banks of Flash devices are available. Each bank is 4 or 8 MBytes wide for a total of 8 or 16 MBytes Flash. The GPCM is used to control the Flash memory. Each bank is controlled by the Chip Select 0 (CS0) or Chip Select 2 (CS2) signal. The Flash memory has boot capability in accordance with the 'Bootbank' jumper setting. The granularity is 16 bits, it means that the minimum size accessible in the Flash memory is two bytes.
Rev. 1.43 User's Guide Typical Option Register: Bit 0-16 17-18 19 20 21-22 23 24-27 28 29 30 31 Field AM Reserved BCTLD CSNT ACS Reserved SCY SETA TRLX EHTR Reserved -> OR0 Value $FFC0 0 00 0 0 00 0 0110 1 0 0 0 = Function Address mask: for 4 MBytes --Buffer control: on Chip select negation time: normal Address to CS setup: 0 --Cycle length: 6 External access termination: external Timing relaxed: off Extended hold time: off --- $FFC0 0068 This example is for a 8MByte VSBC-6862.
VSBC-6862 Rev 1.43 4.2.3. FLASH chip erase Chip erase operation is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm, which is an internal algorithm that automatically programs the array if it is not already programmed before executing the erase operation. During erase, the device automatically defines the erase pulse widths and verifies proper cell margin.
Rev. 1.
VSBC-6862 Rev 1.43 4.3. SDRAM memory This memory is handled by the powerful SDRAM timing machine contained in the MPC-8260. The SDRAM machine provides an interface to synchronous DRAMs, using SDRAM pipelining, bank interleaving, and back-to-back page mode to achieve the highest performance. This controller supports directly all the SDRAM possibilities, like pipelining and interleaving. The VSBC-6862 is supplied with 128 MBytes SDRAM on-board, organized with four 16Mbitsx16 devices.
Rev. 1.43 User's Guide Typical Option Register: Bit 0-16 17-18 19-22 23-25 26 27 28-31 Field AM BPD ROWST NUMR PMSEL IBID Reserved Value $FE00 0 01 0111 011 0 0 0000 Address mask: Bank per device: Row start address bit: Number of Row lines: Page mode select: Int.
VSBC-6862 Rev 1.43 4.4. SRAM memory The VSBC-6862 includes 1 MByte SRAM for fast exchanges with external VME masters. With its backup capability with the VME Stand-By power line, this memory can be also useful to backup critical data. This memory is handled with the GPCM through the Chip Select 9. It is organized with two 16 bits wide chips to achieve a data width of 32 bits.
Rev. 1.43 User's Guide 4.5. Real Time Clock with SRAM memory The VSBC-6862 includes a real time clock device, with as an additional feature, a battery backed 32 kByte SRAM. This 32 kByte SRAM provides a flexible user data storage with retention capability by its SNAPHAT battery pack. This device is connected on an 8 bits wide data path. This device provides also functions like Alarm, Battery Test, and Watchdog function. The GPCM is used to control the Real Time Clock and the battery backed SRAM.
VSBC-6862 Rev 1.43 48T37V partial register map is: Base + $7FFF $7FFE $7FFD $7FFC $7FFB $7FFA $7FF9 $7FF8 $7FF7 $7FF6 $7FF5 $7FF4 $7FF3 $7FF2 $7FF1 $7FF0 With: D7 0 0 0 0 0 ST W WDS AFE RPT4 RPT3 RPT2 RPT1 WDF D6 D5 D4 10 Years 0 0 10M.
Rev. 1.43 User's Guide The Watchdog can be activated by setting the RTC's Watchdog register (internal offset $7ff7) with the desired time-out value. When the Watchdog is active, it decrement its internal counter until 0. To reload the counter, you can either write again the RTC's watchdog register, either toggling the RTCWDI pin. (connected to the 8260's I/O PD12) If the Watchdog counter reachs zero, the M48T37V generate an interrupt to its IRQ pin.
VSBC-6862 Rev 1.43 4.6. IP modules The VSBC-6862 board provides four IP module slots, which are compliant with the ANSI/VITA 4-1995, except the clock timing. (see the following Warning) It provides support for 8 MHz type and DMA modules.
Rev. 1.43 User's Guide The IP interface uses two processor chip selects to cover all IP module spaces. The I/O, ID, and INT spaces are controlled by the Chip Select 4. The memory space is controlled by the Chip Select 5.
VSBC-6862 Rev 1.
Rev. 1.43 User's Guide 4.6.1.
VSBC-6862 Rev 1.43 With: The GCRx registers allow configuration of the IP module main capabilities, as following: ENIRQ bit: When set, it enables interrupt request to the processor. Both interrupt sources, of the IP slot, are controlled with ENIRQ. After system reset, all interrupt sources are disabled. IPF5V bit: Indicates the 5V status on the IP slots. 4.6.3. Interrupt functions Each IP slot is able to provide up to two interrupt sources.
Rev. 1.43 User's Guide 4.6.4. DMA functions The DMA is controlled by the IDMA channels of the MPC-8260. The DCR registers set-up the DMA channels configuration, as following: ENDMA bit: It enables the DMA request to the PowerQUICC II processor, in accordance with the S0 bit definition. After system reset, all DMA request sources are disabled. When this bit is set, the Transmit Clock line for the serial port 4 is not accessible.
VSBC-6862 Rev 1.43 Board control registers The VSBC-6862 contains some registers for general board features. They are mapped in the Chip Select 4 memory map and VME slave A16 memory map as: Local Offset $1001 $1011 VME offset $9 --- Name SRESR SWPR Mode WO RO Description Software Reset Register Switch Position Register With: The SRESR register This register permits to generate by software, Reset signals to the board. Resets can be initiated to the MPC8260, board peripherals, and Flash memory.
Rev. 1.43 User's Guide 4.7. VME operations The VSBC-6862 includes also modules to handle VME operations. There is VME master, slave, interrupter, interrupt-handler and system controller modules. Each module can be considered as an independent module. The next chapters will describe these modules. 4.7.1. Jumpers Some functions are controlled by jumpers for the VME module.
VSBC-6862 Rev 1.43 4.7.3. VME master The VSBC-6862 is VME master A32/A24/A16/D32/D16/D8 The VME master can use two windows to access the VME bus. They are controlled by the UPM, with the chip selects CS6 and CS7. All VME chip select takes a CPU space of 64 MBytes.
Rev. 1.43 User's Guide Typical Option Register: Bit 0-16 17-18 19 20-22 23 24-28 29-30 31 Field AM Reserved BCTLD Reserved Burst inhibit Reserved EHTR Reserved -> Value $FC00 0 00 0 000 1 00000 01 0 OR6-7 = Address mask: --Buffer control: --Burst disabled --One idle clock inserted --- Function for 64 MBytes on $FC00 0102 The UPM C must also be defined. The definition is the same as for the UPM A and UPM B described in the IP modules chapter. The two VME windows have the same VME request level.
VSBC-6862 Rev 1.43 4.7.4. VME slave The VSBC-6862 is slave A16/A24/D32/D16/D8. The board contains an independent slave module. This module doesn't need the local processor to be initialized to be active.
Rev. 1.43 User's Guide The A24 window This window contains Flash, SRAM, and RTC zones. This window occupies 1 MBytes and must be enabled with the VSBA24[WinA24On] bit before use. Its base address into the VME A24 space is defined with the VSBA24 register.
VSBC-6862 Rev 1.43 The VMEA24 Slave window accepts the 'pseudo-RMW' cycles as described on the VME master chapter. We also implement a function to have an local exclusive access to the shared memory. This is useful to keep the memory coherency by avoiding an external VME access between two critical local access. This function is called 'local_RMW' cycle, and is available through the BSCR[local_rmw] bit.
Rev. 1.43 User's Guide 4.7.8. VME system controller The VSBC-6862 can work as a system controller. This function can be enabled or disabled with the Slot1 jumper. When the system controller feature is enabled, the VSBC-6862 provides the following functions: • VME arbiter: SGL, PRI or RRS depending of the VAM register. - In SGL mode: Single Level, the arbiter uses only the BusRequest3 signal from VME. and activates only the BusGrant3 signal.
VSBC-6862 Rev 1.43 4.8. Serial I2C EEPROM 8 kbits of non-volatile memory is provided on the I2C bus. This memory can be used for board initialization and user purposes, they will generally contains some boards specific information like physical Ethernet addresses. Please see the chapter Board initialization for more details . The chip used is a M24C08 and is configured at address 0xb '1 0 1 0 0 x x r/!w' and occupies four addresses on I2C bus. 68 Artisan Technology Group - Quality Instrumentation ...
Rev. 1.43 User's Guide 4.9. Fast Ethernet ports 4.9.1. Transceivers description The two fast Ethernet interfaces come directly from the MPC-8260 processor. The physical layer is achieved with on-board fast Ethernet transceivers. The SMSC-LAN83C183 provides all of the IEEE 802.3u 100Base-TX and ISO802.3 10Base-T Physical Layer (PHY) functions needed for workstations, bridge, router, and switch applications.
VSBC-6862 Rev 1.43 4.9.2. MPC-8260 I/O ports The following table gives the connection to MPC-8260 I/O ports.
Rev. 1.43 User's Guide 4.9.3. Transceivers operations Each transceiver has many registers to handle Fast Ethernet operation. These registers are accessed with set of command on the MII bus. Commands must use a serial format starting with an idle pattern that is a series of at least 32 1's of data, with clock pulses having at least 400ns period. The frame then starts with 0101 for a Write, or 0110 for Read, The next 5 bits are PHY address. The next 5 bits are register address select bits.
VSBC-6862 Rev 1.43 PHY register address 1: 15 Bit NAME 100BASE-T4 14 100BASE-TX full duplex 13 100BASE-TX half duplex 12 10Mb/s full duplex 11 10BASE-T half duplex 10 100Base-T2 full duplex 9 100Base-T2 half duplex 8 :7 6 Reserved MF Preambule suppression 5 Auto negotiation compl.
Rev. 1.43 User's Guide PHY register address 4: 15 Bit NAME Next Page 14 Acknowledge 13 Remote fault 12:10 9 Reserved T4 8 TX_FDX 7 TX_HDX 6 10_FDX 5 10_HDX 4:1 0 Reserved CSMA 802.
VSBC-6862 Rev 1.
Rev. 1.43 User's Guide 4.10.SMC1 and SMC2 serial ports One of these general-purpose serial ports is available on the front panel RJ-45 connector. The other one is available on an internal connector. These serial ports can be typically uses as system console ports. Note that this type of port has no hardware flow control capability. 4.10.1. MPC-8260 I/O ports The following table gives its connection to MPC-8260T I/O ports.
VSBC-6862 Rev 1.43 4.11.SCC serial ports The VSBC-6862 offers four independent serial ports. In synchronous mode, all four ports have independents RX clock signals, but only SCC1 and SCC2 have TX Clocks signals. These ports are directly controlled by the Serial Communication Controllers (SCC) included in the PowerQUICC II. These SCC includes functions like support of many protocols like UART and HDLC, it contains also FIFO buffers: 32-byte deep, and many more powerful options.
Rev. 1.43 User's Guide 4.11.2. RS-422/RS-485/V.35 option These VSBC-6862 ports are compatible with these three modes. The following signals are controlled by the PowerQUICC II: TxD, RxD, TxC, RxC in differential mode CTS, RTS and DCD in RS-232 mode for V.35 As described above, the VSBC-6862 did not provides all defined signals for V.35, it provides all 'transmission signals' but not for example, the loopback or ring indicator signals.
VSBC-6862 Rev 1.43 4.11.3. ACTIS Serial Cable ACTIS can provide a serial cable for these multi-protocol serial ports. Its reference is CAB-V6862SCC-01. This cable connects the VSBC-6862 multi-protocols serial ports (SCC) in RS-232/RS422/RS-485/V.35 mode to a DCE equipment, for example a modem. Connectors: Length: Pinout: Sub-D high-density 15-pin male width max: 31,3mm Sub-D 25-pin male 1.8m Pin function RS-232/V.
Rev. 1.43 User's Guide 4.11.4. MPC-8260 I/O ports The following table gives the connection to MPC-8260 I/O ports.
VSBC-6862 Rev 1.43 4.12.I2C interface The VSBC-6862 provides an I2C interface bus for on-board serial EEPROM accesses and user purposes. For example, this non-volatile memory store the Ethernet addresses for the two Fast Ethernet ports. The serial EEPROM is placed at I2C address 0xb '1 0 1 0 0 x x r/!w' It occupies four addresses. All other addresses can be used for external add-on peripherals. The I2C interface is present on the P4 connector.
Rev. 1.43 User's Guide 5 Summary of board resources 5.1. Chip Select Chip Select CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS9 Port size (bits) 32 64 32 8 16 16 8, 16, 32 8, 16, 32 32 Device Flash bank 0: boot device 0 SDRAM Flash Bank 1: boot device 1 Real Time Clock and SRAM IP ID, I/O + Board registers IP Mem VME window A VME window B SRAM Size 8 MBytes 128 MBytes 8 MBytes 32 kBytes 32 kBytes 32 MBytes 64 MBytes 64 MBytes 1 MBytes 5.2.
VSBC-6862 With: Rev 1.43 Local offset: VME offset: Mode: offset from local CS4 offset from VME A16 slave window, defined with J8 RW=Read/Write, RO=Read only, WO=Write only 5.3. Interrupt sources Interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Source not used VME interrupt-handler IP module D IP module C IP module B IP module A VME mailbox not used The two Ethernet controllers have each one interrupt request line.
Rev. 1.
VSBC-6862 Rev 1.43 5.5. Power description For the majority of the applications, the VSBC-6862 uses only the +5V power supply. Internally, many modules use 3.3V, and the MPC-8260 use also 2.5 or 2.0V. The internal 3.3V, and 2.5V or 2.0V voltages are generated on-board. An internal power fail monitor generates a Power-On Reset signal when the +3.3V line fall below 2.97V. The +12V is used for special protection feature on Flash memory (optional) and some IP modules. The -12V is only used by some IP modules.
Rev. 1.43 User's Guide 5.7. MPC-8260 I/O ports assignment The MPC-8260 processor provides four I/O ports (A, B, C and D) which have the abilities for handling several hardware functions like serial communication interfaces, DMA control handling and general purpose I/Os.
VSBC-6862 Rev 1.
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Rev. 1.43 User's Guide 6 Board initialization The VSBC-6862 must set up the specific hardware organization for the PowerQUICC II processor. This setup must be completed on software initialization to ensure an adequate operation.
VSBC-6862 Rev 1.43 6.2. Reset Word The ResetWord is a 32 bits field read by the PowerQUICC II during Power-On sequence. This word set several important options for the hardware operations. The Reset Word must be located in the bootable device, on the VSBC-6862, it will be in the Flash memory bank, at offset 0.
Rev. 1.43 User's Guide 6.3. MPC-8260 internal registers The MPC-8260 contains some registers to configure for correct operations. Here follows the specific configuration of these registers for the VSBC-6862: Internal Memory Map Register: IMMR This register set the memory map for the MPC-8260 internal registers.
VSBC-6862 Rev 1.43 SIU Module Configuration Register: SIUMCR This register contains bits that configure various features in the SIU module.
Rev. 1.43 User's Guide 6.4. MPC-8260 I/O ports The PowerQUICC II contains 120 I/O pins that are used for communication ports and general purpose I/Os. Many different functions are multiplexed on I/O pins, and need to be defined depending on the board configuration.
VSBC-6862 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 I/O PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 Rev 1.
Rev. 1.
VSBC-6862 Rev 1.43 6.5. Chip select Before accessing a internal peripheral, the corresponding chip select must be initialized. The description of all chip select initializations are described in the Software description. It's important to note the order in which OR0 and BR0 are programmed. When coming out of reset and CS0 is the global chip select, OR0 MUST be programmed AFTER BR0. In all other cases BRx would be programmed after ORx.
Rev. 1.43 User's Guide Serial Number Option (optional) This option specifies the serial number of the product (ASCII terminated by a zero byte). The code for this option is 3, and its minimum length is 1. E.g.: $03 $06 'P' 'R' 'O' 'T' 'O' $00 Revision Option (optional) This option specifies the revision / version of the board. The code for this option is 8, and its length is 2 (Revision/Edition). E.g.
VSBC-6862 Rev 1.43 6.7. Boot code The boot code is mapped as standard PowerPC map. The exception table is located from offset $0100 to $2FFF. With the offset $0100 corresponding to the System Reset Exception. Thus the boot code will start at the offset $0100 of the bootable Flash memory bank. The addresses below $0100 are reserved for the PowerQUICC II reset configuration. By default, the VSBC-6862 is provided with one Flash memory bank factory loaded with the ECMon debugger.
Rev. 1.43 User's Guide 7 Registers definition IPGCRA CS4 + $401 IP General Configuration Register A RW IPGCRB CS4 + $501 IP General Configuration Register B RW IPGCRC CS4 + $601 IP General Configuration Register C RW IPGCRD CS4 + $701 IP General Configuration Register D RW These registers permit to configure general purposes for IP slot x.
VSBC-6862 Rev 1.43 IPDCRA CS4 + $403 IP DMA Configuration Register A RW IPDCRB CS4 + $503 IP DMA Configuration Register B RW IPDCRC CS4 + $603 IP DMA Configuration Register C RW IPDCRD CS4 + $703 IP DMA Configuration Register D RW These register permits to configure the DMA access for IP slot x.
Rev. 1.43 User's Guide IPIVRA CS4 + $481 IP Interrupt Vector Register A RO IPIVRB CS4 + $581 IP Interrupt Vector Register B RO IPIVRC CS4 + $681 IP Interrupt Vector Register C RO IPIVRD CS4 + $781 IP Interrupt Vector Register D RO These registers permit to acknowledge the IRQ for IP slot x.
VSBC-6862 Rev 1.43 SRESR Software Reset Register CS4 + $1001 VME slave + $9 WO This register permits to perform Software or Hardware Reset by software Value Default D8 D9 D10 D11 D12 D13 D14 D15 x x x x x x x x R0 0 R1 0 R2 0 R3 0 Writing this register with the value $1 'connects' the RTC's Watchdog pin to the Power-On Reset Writing this register with the value $3 generates a Reset on Flash Devices Writing this register with the value $6 generates a Hardware Reset on board.
Rev. 1.43 User's Guide BSCR CS4 + $1021 Board Special Configuration Register RW This register permits to access the protection purpose of the Flash memory. This option is available on request.
VSBC-6862 VMBA CS4 + $1051 Rev 1.
Rev. 1.43 User's Guide VMBMA CS4 + $1055 VME Master: A32 Base address for window A RW VMBMB CS4 + $1057 VME Master: A32 Base address for window B RW These register permit to complete the high order address for accesses in A32 mode. D8 D9 D10 D11 D12 D13 D14 D15 Value Default x x VA31 0 VA30 0 VA29 0 VA28 0 VA27 0 VA26 0 VA25 0 With: VA31: VME address A31 ..
VSBC-6862 VHIL CS4 + $1061 Rev 1.43 VME interrupt Handler: Interrupt Level RO This register indicates the current VME interrupt level to acknowledge by reading the corresponding VHV register. D8 D9 D10 D11 D12 D13 D14 D15 Value Default x x IRQ7 x IRQ6 x IRQ5 x IRQ4 x IRQ3 x IRQ2 x IRQ1 x With: IRQ1: ... IRQ7: VME interrupt request level 1 ... VME interrupt request level 7 This register always indicates the current VME IRQ Level, even masked interrupts.
Rev. 1.
VSBC-6862 Rev 1.43 VIVEC VME Interrupter Vector CS4 + $106d VME slave + 7 RW This register contains IRQ level and the vector sent by the VME interrupter. 8260 VME Value Default With: D8 D7 D9 D6 D10 D5 D11 D4 D12 D3 D13 D2 D14 D1 D15 D0 IL2 0 IL1 0 IL0 0 Vec4 0 Vec3 0 Vec2 0 Vec1 0 Vec0 0 IL2-IL0: Vec4-Vec0: IRQ level coded on 3 bits.
Rev. 1.43 User's Guide VSBA24 VME Slave Base Window A24 CS4 + $1069 VME slave + 3 RW This register sets the VME base address for the visible A24 memory window.
VSBC-6862 Rev 1.43 VSWA24 VME Slave Window A24 management CS4 + $106b VME slave + 5 RW This register contains the local offsets for the VME A24 window. 8260 VME Value Default With: D8 D7 D9 D6 D10 D5 D11 D4 D12 D3 D13 D2 D14 D1 D15 D0 x x SRA19 0 x x FLA22 0 FLA21 0 FLA20 0 FLA19 0 FLA18 0 SRA19: corresponding high order local address for SRAM memory. FLA18-FLA22: corresponding high order local addresses for Flash memory.
Rev. 1.43 User's Guide 8 Characteristics Electrical characteristics PARAMETER POWER SUPPLY +5 V (VDD) +12 V -12 V Input voltage Operating Power supply current Icc+5V (without IP modules) Icc+12V (only used by IP modules and Flash protection) Icc-12V (only used by IP modules) MIN TYP MAX UNITS 4.5 V 10.8 -13.2 GND-0.3 - 5.5 13.2 -10.8 VDD+0.
VSBC-6862 Rev 1.43 Performance issues The VSBC-6862 has been designed for providing efficient performance with peripheral connected around the PowerQUICC II processor. The following table provides the respective wait states that should be expected for each access type.
Rev. 1.43 User's Guide 9 Physical board definition 9.1. PCB dimensions 1.7mm 160mm Figure 22: PCB dimensions 113 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.
VSBC-6862 Rev 1.43 9.2. Front panel Figure 23: Front panel 114 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.
Rev. 1.43 User's Guide 10 Software available Thanks to ECRIN Automatismes, many software packages are already available for the VSBC-6862. ECRIN is our sister company and work together with ACTIS to provide full solution to our customers. All software requests can be directly addressed at ECRIN. (see chapter Technical support) 10.1.Debug tools Many debug tools are available for debugging. These tools use the JTAG port of the 8260 to access low level resources.
VSBC-6862 Rev 1.43 The boot time is less then 1 second. Then, when typing the 'Return' key, the 'ECMon>' prompt will be displayed. The default radix for all commands is hexadecimal. You can use an explicit prefix to specify the radix as: hexadecimal decimal binary ASCII 0x 0d 0b ' The last command can be recalled typing the 'Control-A' sequence. The command line can be erased typing the 'Control-X' sequence. 10.2.1. Command description All current commands are described here in alphabetic order.
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VSBC-6862 Rev 1.43 mmap Function : Syntax : Display memory map mmap mmb, mmw, mml Function : Syntax : Options : Modify the contents of memory (byte-value) mmb
[ { | } ] - starting address - data items - '+' to go on next address - '-' to go on previous address - '.Rev. 1.
VSBC-6862 Rev 1.43 10.2.3. Typical example The following example will describe the procedure to use the second Flash memory bank as user's boot device: Assuming the new software in this example is less than 64k.
Rev. 1.43 User's Guide 11 Hardware available One of the main advantage of the VSBC-6862 is his versatility. Through its IP and/or VME slots, the VSBC-6862 can be used in quantities of purposes. Here follows the customization possibilites with ACTIS's modules: 11.1.List of ACTIS's IP modules The VSBC-6862 can expand his functions by the mean of the IP modules. Up to four IP modules can be plugged on this board. A choice of these modules is available by ACTIS Computer, and the most used are described above.
VSBC-6862 Rev 1.43 LAN-15 MIL-STD-1553 Bus controller (BC), Remote terminal (RT), and Bus monitor (MT) with 64K x 16 bit of RAM (to support complex MT or BC applications), compatible with other IP using the DDC ACE controller LAN-200 Fast Ethernet™ IEEE802.3u Controller with on-board 128 KBytes Fast SRAM buffer, 8 and 32 MHz compatible, DMA transferts supported, on-board 10BASE-T and 100BASE-TX transceivers.
Rev. 1.43 User's Guide 11.2.List of ACTIS's 6U transition modules The IP modules provides many functions, some of these functions need special connectors or lot of I/O ports. ACTIS provide transition modules for all its IP modules and cables to provide professional connectors on front panels. A choice of ACTIS transition modules is described above. Reference Description IO-32 Terminal Block with LED for 32 singles wires for 2 INP-16, OUT-16 (New version with Light Pipes), I/O connectors included.
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Rev. 1.43 User's Guide 12 Technical support Should you encounter any trouble during installation or hardware operation of your VSBC-6862, please contact our Technical support: • Email : support@actis-computer.com In order to solve your problem as quickly as possible, please check and note the following beforehand: • VSBC-6862 serial number. • Model name and number of PC Card and IP module. • OS version such as OS-9, pSOS, VxWorks, etc. • Software driver and application revisions.
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Rev. 1.43 User's Guide 13 Ordering information VSBC-6862/200-128-16 VME board with MPC-8260 @ 200 MHz 128 MBytes SDRAM, 16 MBytes Flash memory, and four serial ports VSBC-6862/200-128-EK Engineering Kit VSBC-6862, contains documentation, support CD-ROM, four IP cables, four multi-protocol serial cables. CAB-RJ45-DB9 Adaptor cable with RJ-45 and DB-9 female in RS-232, DTE mode CAB-V6862-SCC-01 Adaptor cable with DB-15 high density male and DB-25 male in RS-232/RS-422/RS485/V.
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Rev. 1.43 User's Guide 14 OEM Warranty ACTIS Computer, warrants your VSBC-6862 board against any defect in material and workmanship, under normal use, for a period of three years from the date of purchase. In the event this product is found to be defective within the warranty period, ACTIS Computer will, at its option, repair or replace the defective single board computer. This warranty is void if: a) The board was operated or stored under condition of abnormal use or maintenance.
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Rev. 1.43 User's Guide 15 Appendix 15.1.Application examples with the VSBC-6862 15.1.1. Example A: Application with VME boards This example represents the VSBC-6862 used in a standard VME rack with other VME boards and transition modules. In this configuration, the VSBC-6862 is VME master and can also be configured in system controller mode to arbiter the bus access for other masters.
VSBC-6862 15.1.2. Rev 1.43 Example B: Application with non-VME boards The SBC-6860 is a single board computer, VME bus tolerant from ACTIS. This board provides two PC-Cards slots, one ISDN port, one multi-protocol serial port, two IP slots, and more...
Rev. 1.43 User's Guide 15.1.3. Example C: Application in stand-alone The VSBC-6862 can be used in stand-alone mode. The following picture illustrates the VSBC-6862 equipped with four UCC-08A/B IP modules, which provides each eight synchronous or asynchronous serial ports. For more convenience, we added four SC-08DB transition modules to have standard DB-25 connections on front panel.
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Rev. 1.43 User's Guide 16 Index Board configuration jumpers .............................................................................................................................................. 25 software description ........................................................................................................................... 60 Board initialization .................................................................................................................................
VSBC-6862 Rev 1.43 jumpers .............................................................................................................................................. 27 overview............................................................................................................................................. 18 software description ........................................................................................................................... 76 Termination resistors ..............
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