User Manual

11. RGMII interface connection example
RGMII signals from the host processor
RGMII signals from RGMII module pin assignments
Signals
Pin descriptions
Pin Type
Pin
Signals
Pin Type
GTXD3
RGMII Transmit data bit 3
Output
13
GRXD_I_3
Input
GTXD2
RGMII Transmit data bit 2
Output
16
GRXD_I_2
Input
GTXD1
RGMII Transmit data bit 1
Output
15
GRXD_I_1
Input
GTXD0
RGMII Transmit data bit 0
Output
18
GRXD_I_0
Input
GTXEN
RGMII Transmit enable
Output
20
RXDV_I
Input
GTXCLK
RGMII 125MHz TXCLK
Output
17
GRXCLK_I
Input
GRXCLK
RGMII receive clock
Input
21
GTXCLK_O
Output
1K Pull down resistor
24
GTXCLK_I
Input
GRXDV
RGMII receive data valid
Input
25
GTXEN_O
Output
GRXD3
RGMII Receive data bit 3
Output
27
GTXD_O_3
Output
GRXD2
RGMII Receive data bit 2
Output
29
GTXD_O_2
Output
GRXD1
RGMII Receive data bit 1
Output
28
GTXD_O_1
Output
GRXD0
RGMII Recevie data bit 0
Output
30
GTXD_O_0
Output
1k Pull down resistor
33
25M_GPHY
Output
12. MDIO/MDC
QT3840BC has a MDIO master controller so it can be used to manage any MDIO slave device on the host
board. The two signals are provided on pin 11 and pin 12 of the mPCIe connector. If there is no need for
QT3840BC to be the MDIO master, then pull down both MDC and MDIO signal to ground with 1K ohm
resistor.
13. 25M_GPHY
25M_GPHY is a free running 25MHz clock generated by QT3840BC.