User`s manual

Chapter 4: BIOS
4-15
CPU Cache Control
DCU Prefetcher (Available when supported by the CPU.)
The CPU fetches the cache line for 64 bytes if this option is set to Disabled.
The CPU fetches both cache lines for 128 bytes as comprised if Enabled. The
options are Disabled and Enabled.
IP Prefetcher (Available when supported by the CPU.)
Select Enabled to use CPU Cache Line IP Prefetch. The options are Disabled
and Enabled.
Direct Cache Access (Available when supported by the CPU.)
Set to Enable to route inbound network IO trafc directly into processor caches
to reduce memory latency and improve network performance. The options are
Disabled and Enabled.
DCA Delay Clocks (Available when supported by the CPU.)
This feature allows the user to set the clock delay setting from snoop to prefetch
for Direct Cache Access. Select a setting from 8 (bus cycles) to 120 (bus cycles)
(in 8-cycle increment). The default setting is 32 (bus cycles).
I/ODeviceConguration
Access the submenu to make changes to the following settings.
KBC Clock Input
This setting allows you to select clock frequency for KBC. The options are 6MHz,
8MHz, 12MHz, and 16MHz.
Serial Port A
This setting allows you to assign control of serial port A. The options are Enabled
(user dened), Disabled, and Auto (BIOS- or OS- controlled).
Base I/O Address
This setting allows you to select the base I/O address for serial port A. The op-
tions are 3F8, 2F8, 3E8, and 2E8.
Interrupt
This setting allows you to select the IRQ (interrupt request) for serial port A. The
options are IRQ3 and IRQ4.