Specifications

AR-B1564 User¡¦s Guide
3-12
Name Description
-MASTER [Input] The MASTER is the signal from the I/O processor which
gains control as the master and should be held low for a
maximum of 15 microseconds or system memory may be
lost due to the lack of refresh
-MEMCS16
[Input, Open collector]
The Memory Chip Select 16 indicates that the present
data transfer is a 1-wait state, 16-bit data memory
operation
-IOCS16
[Input, Open collector]
The I/O Chip Select 16 indicates that the present data
transfer is a 1-wait state, 16-bit data I/O operation
OSC [Output] The Oscillator is a 14.31818 MHz signal
-ZWS
[Input, Open collector]
The Zero Wait State indicates to the microprocessor that
the present bus cycle can be completed without inserting
additional wait cycle
Table 3-4 PC/104 ISA Bus Pin Assignment
3.2.7 CPU Setting
The AR-B1564 accepts many types of 586 microprocessor, such as INTEL Pentium, AMD-K5, AMD-K6, and
CYRIX 6x86. All of these CPUs include an integer processing unit, floating-point processing unit, memory-
management unit, and cache. They can give a two to en-fold performance improvement in speed over the 486
processor, depending on the clock speeds used and specific application. Like the 486 processor, the 586
processor includes both segment-based and page-based memory protection schemes. Instruct processing time
has reduced by on-chip instruction pipelining. By performing fast, on-chip memory management and caching, the
586 processor relaxes requirements for memory response for a given level of system performance.
(1) CPU Logic Core Voltage Select (SW3)
Figure 3-19 SW3: CPU Logic Core Voltage
SW3-1 SW3-2 SW3-3 SW3-4 SW3-5 SW3-6 Voltage
OFF ON OFF OFF OFF -- Setting A
ON ON OFF OFF OFF -- Setting B
ON OFF OFF ON OFF -- Setting C
OFF ON OFF ON OFF -- Setting D
OFF ON ON ON OFF -- Setting E
ON ON ON ON OFF -- Setting F
Table 3-5 SW3: CPU Logic Core Voltage
(2) System Base Clock & CPU Clock Multiplier (SW1)
Figure 3-20 SW1: CPU Clock Multiplier