User`s manual

I/O SERVER User’s Manual Industrial PC
__________________________________________________________________
________________________________________________________________________
Acromag, Inc. Tel:[phone] Fax:[phone] Email:[e-mail] http://www.acromag.com
36
The IOS Interrupt Pending Register is used to individually identify
pending IOS module interrupts or a pending carrier board generated
interrupt as a result of IOS module time out access. If multiple IOS module
interrupts are pending, software must determine the order in which they are
serviced.
MSB
D7 D6 D5 D4 D3 D2 D1
LSB
D0
IOS D
Int1
Pend
IOS D
Int0
Pend
IOS C
Int1
Pend
IOS C
Int0
Pend
IOS B
Int1
Pend
IOS B
Int0
Pend
IOS A
Int1
Pend
IOS A
Int0
Pend
MSB
D15 D14 D13 D12 D11 D10 D9
LSB
D8
Not Used
(bits read as
logic “0”)
Time Out
Interrupt
Pend
Not Used (bits read as logic “0”)
All Bits
IOS Interrupt
Pending
(Read)
A bit will be a “1” when the corresponding interrupt is
pending. A bit will be a “0” when its corresponding
interrupt is not
pending. Polling this bit will reflect the
IOS module’s pending interrupt status, even if the IOS
modules interrupt enable bit is set to “0”.
Reset Condition: Set to "0". An IOS module pending
interrupt bit will be cleared if its corresponding interrupt
request signal is inactive.
The Clock Control Register is used to select the operational frequency
of individual IOS modules. A “0” (default) indicates that the IOS module is
supplied with an 8MHz clock. A “1” indicates that the IOS module is
supplied a 32MHz clock. A reset will set all bits of this register to “0”.
MSB
D15 D4 D3 D2 D1
LSB
D0
Not Used IOS D
CLK
IOS C
CLK
IOS B
CLK
IOS A
CLK
The Interrupt space for each IOS module is fixed at two 16-bit words.
Interrupt 0 select space is read, typically by an interrupt service routine, to
respond to an interrupt request via the IOS Module’s INTREQ0* signal.
Likewise interrupt 1 select space is read to respond to an interrupt request
via the IOS Module’s INTREQ1* signal. An access to an interrupt select
space results in the IOS module serving up an interrupt vector. In addition,
access to the interrupt space will cause some IOS modules to release their
interrupt request. See each IOS module’s User Manual for details.
IOS Interrupt Pending
Register - (Read, PCIBar2 +
02H
)
Clock Control Register -
(Read/Write, PCIBar2 +
018H
)
IOS Module Interrupt Space
- (Read Only)