User`s manual

I/O SERVER User’s Manual Industrial PC
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34
PCIBar3
+
(Hex)
High Byte
D15 D08
Low Byte
D07 D00
PCIBar3
+
(Hex)
0000001
↓
07FFFFF
IOS A
Memory Space
0000000
↓
07FFFFE
0800001
↓
0FFFFFF
IOS B
Memory Space
0800000
↓
0FFFFFE
1000001
↓
17FFFFF
IOS C
Memory Space
1000000
↓
17FFFFE
1800001
↓
1FFFFFF
IOS D
Memory Space
1800000
↓
1FFFFFE
2000001
↓
3FFFFFF
Not Used
2000000
↓
3FFFFFE
1. The board will return “0” for all addresses that are not used.
The IOS carrier board’s base addresses are determined through the
PCI Configuration Registers. The addresses given in the memory map are
relative to the base addresses (PCIBar2, PCIBar3) of the IOS Carrier as
shown in Table 5.2. The addresses within each IOS module are specific to
that IOS module. Refer to the IOS module’s User Manual for information
relating to the IOS specific addressing.
The Carrier registers, IOS Identification (ID) spaces, IOS Input/Output
(IO), IOS Interrupt spaces, and Memory (MEM) spaces are accessible via
the PCI bus space as given in Tables 5.3. A 32-bit PCI bus access will
result in two 16-bit accesses to the IOS module. A 16-bit or 8-bit PCI bus
access results in a single 16-bit or 8-bit access to the IOS module
respectively.
The Carrier Board Status Register reflects and controls functions
globally on the carrier board. This includes monitoring the IOS Error
signal, enabling, disabling, or monitoring IOS and timeout interrupts,
performing a software reset for the carrier board and IOS modules, and
identifying if memory space is enabled.
Table 5.3: IOS Carrier Board
Memory Map Continued
Carrier Status/Control
Register - (Read/Write,
PCIBar2 + 00H
)