User`s manual

I/O SERVER User’s Manual Industrial PC
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The IOS Carrier and subsequently the IOS modules must be accessed
thought the PCI bus. The PCI bus is defined to address three distinct
address spaces: I/O, memory, and configuration space. The IOS modules
can be accessed via the PCI bus memory space only.
The IOS carrier is a Plug-and-Play PCI board. As a Plug-and-Play card
the IOS Carrier board’s base address and system interrupt request line are
assigned by system software upon power-up via the configuration
registers. A PCI bus configuration access is used to access a PCI card’s
configuration registers.
When the computer is first powered-up, the computer’s system
configuration software scans the PCI bus to determine what PCI devices
are present. The software also determines the configuration requirements
of the PCI card.
The system software accesses the configuration registers to determine
how many blocks of memory space the carrier board requires. It then
programs the carrier board’s configuration registers with the unique
memory address range assigned.
The configuration registers are also used to indicate that the IOS carrier
board requires an interrupt request line. The system software then
programs the configuration registers with the interrupt request line
assigned to the IOS carrier.
The PCI bus is designed to recognize certain I/O accesses initiated by
the host processor as a configuration access. Configuration uses two 32-
bit I/O ports located at addresses 0CF8 and 0CFC hex. These two ports
are:
• 32-bit configuration address port, occupying I/O addresses 0CF8
through 0CFB hex.
• 32-bit configuration data port, occupying I/O addresses 0CFC through
0CFF hex.
Configuration space, shown in Table 5.1, is accessed by writing a 32-bit
long-word into the configuration address port that specifies the PCI bus,
the carrier board on the bus, and the configuration register on the carrier
board being accessed. A read or write to the configuration data port will
then cause the configuration address value to be translated to the
requested configuration cycle on the PCI bus. Accesses to the
configuration data port determine the size of the access to the
configuration register addressed and can be either an 8, 16, or 32-bit
operation.
Any access to the Configuration address port that is not a 32-bit access
is treated like a normal computer I/O access. Thus, computer I/O devices
using 8 or 16-bit registers are not affected because they will be accessed
as expected.
The PCI specification requires software driven initialization and
configuration via the Configuration Address space. This PCI carrier board
provides 256 bytes of configuration registers for this purpose. The PCI
carrier board contains the configuration registers, shown in Table 5.2, to
facilitate Plug-and-Play compatibility.
5.0 ACCESSING THE
IOS CARRIER
PCI Configuration Address
S
p
ace
PCI Configuration
Transactions
PCI Confi
g
uration Re
g
isters