Service manual

LUMISCAN ACR-2000 SERVICE MANUAL - SECTION 4.0 THEORY OF OPERATION
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4.5 Sub-System Operation
4.5.1 DATA CONTROL BOARD (DCB)
The DCB is a standard size PC/XT board occupying 32K bytes of memory space and 24 bytes of I/O space.
It supports 8-bit data transfers only and has multiple interrupt capability. The physical memory consists of
a single, 72-pin SIMM with 16MB.
Image memory is accessible through a 32KB window. This window can be positioned on any 32KB
boundary within the standard 1MB DOS address space by means of five DIP switches on the DCB.
Memory page selection is accomplished through a Bank register.
The image memory is accessible at all times including during image acquisition. An arbiter controls access,
giving the data writes priority over bus access. If necessary the PC bus IOCHRDY signal is asserted to
delay the bus access. The image memory should never be written to from the bus during image acquisition.
During image acquisition a separate 24-bit counter selects sequential byte addresses for each data write;
counting always starts at address zero. Address counting is only enabled when SCAN is true, and is reset to
0 when SCAN changes from false to true. The counter can be read at any time.
The control registers are mapped into the I/O addresses 100 hex through 117. These locations are fixed
and can be changed only by changing the firmware. The DCB allows the selection of three alternate
mapping of the I/O registers by means of a DIP switch.
In addition to image memory there are 64KB of memory on the Data Acquisition board which are
accessible through the DCB. This memory is where the calibration and lookup tables are located and is
fully R/W accessible, but only while not scanning. Access is sequential through a 16-bit I/O register. The
memory is organized on the Data Acquisition board as eight tables of 4K x 16 bits each. The sequential
access can begin at the beginning of any one of the eight tables by means of a 3-bit LUT bank select field
and an Autoincrement Reset bit. Accesses can extend beyond the selected bank; the bank register will
autoincrement also.
The DCB can interrupt at levels IRQ3 through IRQ7 (jumper selectable). There are four possible interrupt
sources; each one can be separately enabled and cleared.