User guide

The hardware stack lives in page one (&0100 to &01FF). Certain operations performed using the zero page
addressing mode (relating to memory locations &0000 to &00FF) operate much more quickly than do the
same instructions applied to any other part of the memory map.
As you can understand, this design dictates that RAM will be at the bottom end of memory and (EP)ROM
will be at the top; though some systems (such as the Acorn FileStores) copy the entire firmware to RAM at
startup, and then page out the ROM entirely. This is because RAM can have a faster access time than
EPROMs...
The 6502 instruction set is well documented on-line.
Briefly:
ADC ADd with Carry CPY ComPare with Y register PLP PulL Processor status from the stack
ADC ADd with Carry DEC DECrement ROL ROtate Left
ASL Aritmetic Shift Left DEX DEcrement X register ROR ROtate Right
BCC Branch if Carry Clear DEY DEcrement Y register RTI ReTurn from Interrupt
BCS Branch if Carry Set EOR logical Exclusive OR RTS ReTurn from Subroutine
BEQ Branch if EQual INC INCrement SBC SuBtract with Carry
BIT test BITs INX INcrement X register SEC SEt Carry
BMI Branch if MInus INY INcrement Y register SED SEt Decimal mode
BNE Branch if Not Equal JMP absolute JuMP SEI SEt Interrupt disable
BPL Branch if PLus JSR absolute Jump to SubRoutine STA STore Accumulator
BRK BReaK LDA LoaD Accumulator STX STore X register
BVC Branch if oVerflow Clear LDX LoaD X register STY STore Y register
BVS Branch if oVerflow Set LDY LoaD Y register TAX Transfer Accumulator to X register
CLC CLear Carry LSR Logical Shift Right TAY Transfer Accumulator to Y register
CLD CLear Decimal mode NOP No OPeration TSX Transfer processor Status to X register
CLI CLear Interrupt disable ORA logical OR (with Accumulator) TXA Transfer X register to Accumulator
CLV CLear oVerflow PHA PusH Accumulator to the stack TXS Transfer X register to processor Status
CMP CoMPare PHP PusH Processor status to the stack TYA Transfer Y register to Accumulator
CPX ComPare with X register PLA PulL Accumulator from the stack
The CMOS version adds:
BBR# Branch if Bit # Reset (clear) BBS# Branch if Bit # Set BRA BRanch Always
PHX PusH X register to the stack PHY PusH Y register to the stack PLX PulL X register from the stack
PLY PulL Y register from the stack RMB# Reset (clear) Memory Bit # SMB# Set Memory Bit #
STP SToP STZ STore Zero (to address specified) TRB Test and Reset memory Bit
TSB Test and Set memory Bit WAI Wait (for interrupt)
For more details, I will refer you to http://www.6502.org/
Within 6502asm, you can enter the instructions in upper case or lower case, as suits you.
For more advanced users, the instruction set recognised is loaded from a file (“opcode.dat”), so you could
alter several of the mnemonics if you desire – for example to ‘correct’ how the processor status register is
called ‘P’ in the stack instructions and ‘S’ in the transfer instructions; or to alias ‘ADD’ and ‘SUB’ to ‘ADC’
and ‘SBC’ respectively...
It will not be possible to include support for the 65CE02 because of major design differences (16 bit stack
pointer, additional addressing modes, a ‘Z’ register...).
The ‘Exx’ instructions at the end (all opcode &xB) are specific to AmélieEm; if you wish to use 6502asm for
other purposes, you can safely remove these instructions.
Note that there is a clash with the instruction &CB. This is used as a breakpoint instruction in AmélieEm, and
it is also the WAI instruction on CMOS processors. This is not seen as a problem as the emulator only
supports the NMOS instruction set.
6502asm user guide – prerelease version
page 5