User guide

Absolute indirect
JMP (<address>)
This mode is only available for a specific type of JMP instruction.
The contents of the address pointed to are read, and this in turn becomes the JMP address.
For example:
If &F000 was &A000...
JMP (&F000)
JMP will look at &F000 and ‘see’ &A000. Instead of jumping to &F000, it will indirect, and
we’d jump to &A000.
Example:
JMP (&0F00)
Amélie’s BIOS makes extensive use of this for interrupt and event vectoring, by indirecting
though a known location, we only add a few extra cycles (and waste five bytes). The upside is that
the application code can intercept the interrupt handling at various points.
Additionally, if you look at the BIOS startup code (from rst_vector), you’ll see that the BIOS sets
up a dummy “just in case” interrupt handler while the hardware is set up, and then the proper
interrupt handler is put in place after the hardware has been initialised. Without indirect jumps,
such things would not be possible.
Zero-page absolute indirect
<instruction> (<address>)
This mode is only available on the CMOS versions of the processor. The address specified is a
location in zero page which points to a two-byte effective address.
This is provided on the 65C02 for use with ADC, AND, CMP, EOR, LDA, ORA, SBC, and STA.
Support for four-byte instructions
The 65C02 provides use with a number of instructions that are correctly four characters in length:
BBR0 BBR1 BBR2 BBR3 BBR4 BBR5 BBR6 BBR7 BBS0 BBS1 BBS2 BBS3 BBS4 BBS5 BBS6 BBS7
RMB0 RMB1 RMB2 RMB3 RMB4 RMB5 RMB6 RMB7 SMB0 SMB1 SMB2 SMB3 SMB4 SMB5 SMB6 SMB7
It was intended that there be a translation table to read these four-character instructions and convert them to
three-character versions. This is still ‘in the works’ as it tended to break a lot more than it would have fixed
(because of the assumption of three-character instructions, which was fine for original 6502 code).
There is a work-around. The assembler will recognise these instructions if you omit the middle letter, so that
an instruction such as BBR3 will become BR3. Here is the above table in 6502asm-friendly format:
BR0 BR1 BR2 BR3 BR4 BR5 BR6 BR7 BS0 BS1 BS2 BS3 BS4 BS5 BS6 BS7
RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 SB0 SB1 SB2 SB3 SB4 SB5 SB6 SB7
If you absolutely require the four-character versions to be supported, please get in touch.
6502asm user guide – prerelease version
page 15