Service manual

Chapter 5 E01S Fault finding
FileStore Service Manual 67
4.4 Sequential Circuits
There are four sequential circuits in FileStore:
 RAM refresh
 ROM/RAM latch
 Inton/Intoff
 Econet Clock
These are described below.
4.4.1 RAM Refresh
During every op-code fetch the processor activates (high) the Sync line IC16 pin 7. This has
the effect of turning IC21 output pin 11 into the inverse of IC11 pin 8. IC11, the LS57, is
wired as a divide by 60 frequency counter. Upon receipt of 30 φ2 cycles, the QC output goes
high, changing on the falling edge of φ2. This change occurring with sync high will make the
K input of the JK IC6 low. Upon receipt of the falling edge of the not φ2 clock, the Ready
signal to the processor will go low and the clear signal to the LS57 will go high. This causes
two operations to occur: one is that when the processor sees Ready going low during the
same cycle as sync going high the processor will wait in its current state and will remain in
that state until Ready goes high. The second operation that occurs is that the Clear pin of the
frequency divider has become active (high). This means that the counting of the following 30
cycles of φ2 before changing state (high for 30 cycles, low for 30 cycles – divide by 60) is
stopped and the QC output is taken low which in turn takes the K input of IC6 high. On the
falling edge of not φ2 Ready goes high and the processor is running again.
The effect of all this on CAS is that the two open collector outputs from IC21 pins 8 and 11
swap control of the CAS signal during this process. At the start of the cycle IC21 pin 8 is low
due to φ2. As φ2 goes low QC of IC11 is clocked high which, along with a high sync, IC21
pin 11 will go low. On the next rising edge of φ2 the Ready signal on the processor will go
low. At the same time IC11 will be cleared which will take IC21 pin 11 high. The same rising
edge of φ2 will cause IC21 pin 8 to go low. See Fig 3 for details.