Service manual

Chapter 5 E01S Fault finding
FileStore Service Manual 66
After the system is powered-up, whenever the device is accessed the ,CE is taken low when
the address strobe (AS) is valid (high) /CE is initialised by the write-only latch at &FC08
IC14 pin 15. The address strobe is decoded as &FC00 from 12 and IC17. The memory
address is latched in on the falling edge of the AS.
When reading from the CMOS RAM within the 6818 (IC1) the RTC R/W line is held high
and the data is read on the rising edge of DS. DS is decoded as &FC04 by IC12 and IC17.
The /CE is removed at the end of the access by IC14 pin 15 going low and clearing the base
of Q2 low, hence /CE goes high.
When writing the only difference from the read cycle is that DS is held high while R/W is
strobed,
allowing data to be written to the CMOS RAM in the 6818 (IC1) on the rising edge of R/W.
Refer to Fig 2 for details.
4.3.2 Figure 2: RTC Read/Write timing
The frequency of the internally-generated time base is controlled by the crystal (X1) and the
components R3, R6, C1, C3 and C4. In test mode TP1 is used to set the frequency. Fine
adjustment is provided by C2. An internal timer is programmed by system software to
generate regular interrupts for operating system service routines.
NOTE
A modification has been made to the circuit that prevents spurious writes to the memory of
the RTC. This is implemented by gating /CE off the rising edge of AS so that /CE IC1 pin 13
only goes low when AS goes high. The synchronising of /CE and AS is carried out by
ICmod.