Service manual

Chapter 4 E20 Circuit description
FileStore Service Manual 43
NPGFC (not-page &FC, pin 10) is a signal decoded from the top 8 system address lines (A8
to A15). NPGFC is an active-low signal which is low when the address high byte is &FC, i.e.
when the full address is &FC00 to &FCFF. Four locations in this range are used by the
Winchester system: &FC40 to &FC43 inclusive, see section 11.6.1.
A0 to A7 (address low, pins 27 to 34) are the bottom 8 system address lines.
D0 to D7 (system data bus) are the bi-directional data lines. Direction determined by R/NW.
The data lines use buffered, and the buffer enabled only when NPGFC is active.
Pins 1,3,5,7,9,11,13,15,17 and 26 are 0V.
2MHz Bus Connector pinout are as follows:
Signal Pin Pin Signal
0V 1 2 R/NW
0V 3 4 2MHz
0V 5 6 For other applications
0V 7 8 NIRQ
0V 9 10 NPGFC
0V 11 12 For other applications
0V 13 14 NRST
0V 15 16 For other applications
0V 17 18 D0
0V 19 20 D2
0V 21 22 D4
0V 23 24 D6
0V 25 26 0V
0V 27 28 A1
0V 29 30 A3
0V 31 32 A5
0V 33 34 A7
4.6 Winchester Disc Host Adaptor
In conjunction with the following description, reference should do made to the Winchester
Disc Host Adaptor circuit diagram in the appendix.
The Winchester Disc Host Adaptor is an interface between the SASI/SCSI interface and the
2MHz expansion Bus. It consists of address decoding and handshake control, buffering of the
signals in either direction, and termination.
4.6.1 Address decoding and handshaking
The Host Adaptor decodes 4 locations in the host microcomputer‘s page FC I/O space. Those
four locations are as follows:
Address Read Write
&FC40 data data (direction determined by R/NW)
&FC41 status -
&FC42 - select
&FC43 - enable IRQ
Page FC is decoded in the host system and this is available to the Host Adaptor as NPGFC
(not-page FC). NPGFC is synchronised with 2MHzE by de-glitch circuit (half of IC10) and
the clean signal is labelled CNPGFC (pin 5, IC10).