Service manual

Chapter 4 E20 Circuit description
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The prescribed sequence is from bus free to selection to one or more of the information
transfer phases to bus free again.
There are no restrictions on the order of information transfer phases, and a phase will often
follow itself, e.g. two data phases one after the other.
A typical sequence would be:
 bus free
 select controller - selection phase
 transfer command bytes - command phase
 transfer data bytes (if necessary) - data in/out phase
 status phase
 message phase
The phases are as follows:
4.3.1 Bus free phase
Indicates that the bus is available for use. The bus free phase is indicated by all control
signals described in the previous section being deasserted. If SEL and BSY and RST are not
asserted, that is sufficient to guarantee bus free.
4.3.2 Selection phase
Allows the initiator to select the target. After detecting bus free, the initiator asserts SEL. The
target detects SET asserted and BSY and I/O deasserted, and responds by asserting BSY. The
initiator deselects SET and may then change the data signals.
4.3.3 Information transfer phases
Allow transfer of information across the bus. There are several different types of information
transfer phase, and the type is determined by, MSG, C/D and I/O. The information transfer
phase is shown below:
Signals
MSG C/D I/O Phase name Direction of information transfer
1 1 1 data out phase initiator to target
1 1 0 data in phase target to initiator
1 0 1 command phase initiator to target
1 0 0 status phase target to initiator
0 0 1 message out phase initiator to target (not used)
0 0 0 message in phase target to initiator
All signals active-low: 0=assertion
1=deassertion
The information transfer phases use the REQ/ACK handshake to control information transfer
each REQ/ACK allows the transfer of 1 byte. The handshake sequence is: