Service manual

Chapter 4 E40S/E60S Circuit description
FileStore Service Manual 95
4. E40S/E60S Circuit description
Read this chapter in conjunction with the circuit diagrams for Stacking FileStore E40S and
E60S in Appendix E at the back of this manual.
4.1 Bus phases
The bus has several distinct operational phases and cannot be in more than one of these
phases at any given time.
Bus phases occur in a prescribed sequence. The reset condition can interrupt any phase and is
always followed by bus free. Any other phase can also be followed by the bus free phase.
The prescribed sequence is from bus free to selection to one or more of the information
transfer phases to bus free again.
There are no restrictions on the order of information transfer phases, and a phase will often
follow itself, that is there will be two data phases, one after the other.
A typical sequence would be:
 bus free
 select controller - selection phase
 transfer command bytes - command phase
 transfer data bytes (if necessary) - data in/out phase
 status phase
 message phase
The phases are as follows:
4.1.1 Bus free phase
Indicates that the bus is available for use. The bus free phase is indicated by all control
signals described in the previous section being deasserted. If SEL, BSY and RST are not
asserted, that is sufficient to guarantee bus free.
4.1.2 Selection phase
Allows the initiator to select the target. After detecting bus free, the initiator asserts SEL. The
target detects SEL asserted, and BSY and I/O deasserted, and responds by asserting BSY.
The initiator deasserts SEL and may then change the data signals.
4.1.3 Information transfer phases
Allow transfer of information across the bus. There are several different types of information
transfer phase, and the type is determined by MSG, C/D and I/O.