Service manual

Service Manual
CAM map xxx.yyyy The identifier at physical
page xxx was not equal
to that at logical page yyyy
when they should be
mapped together.
CAM pmk xxx.yyyy The data found at logical
page yyyy was the same
as that at physical page
xxx, but was not the
expected value (ie the data
had become corrupt)
CAM als xxx.yyyy Physical page xxx was
mapped at logical page
yyyy as well as in it's
proper place.
CAM abo xxx.yyyy When physical page xxx
was mapped at logical
page yyyy, MEMC failed to
map anything at that logical
page at all, so a data
transfer abort occurred.
In addition to these reported errors, unexpected
processor traps may occur – either the wrong trap when a
data abort was expected, or a trap occurring at an
unexpected time. These are indicated by one of the
following messages:
RST @ xxxxxxx Reset
UDF @ xxxxxxx Undefined
instruction
SWI @ xxxxxxx Software interrupt
PAB @ xxxxxxx Instruction fetch
abort
DAB @ xxxxxxx Data transfer abort
ADX @ xxxxxxx Address exception
IRQ @ xxxxxxx Interrupt
FIQ @ xxxxxxx Fast Interrupt
with xxxxxxx indicating the address at which the
trap occurred.
These are extremely unlikely to occur, and although they
may be caused by a processor fault are most likely to be
due to an earlier failure (eg a RAM failure causing a
misread data abort vector) causing the processor to
execute code from arbitrary addresses, with
unpredictable results.
PPL test
This is an additional MEMO test which exercises the
memory protection features. Like the CAM test, it relies
on page zero memory to store vectors. It is announced as
PPLs:
which may be displayed as
PPLs: skipped
if previous RAM tests failed.
The test sets the various page protection levels (0 to 3)
and performs reads and writes with MEMC in both
Supervisor and user mode. All code actually executes in
ARM mode 0 (Supervisor), using the Translate flag to
indicate to MEMC that user mode access is required.
Operating system mode is not currently tested. Faults
may be displayed using a message of the form
PPL bad x.y.zzzz
where x is the page protection level tested (0 to 3), zzzz
is the physical page tested and y is the protection found
to be present displayed as a bitmap:
1000 user mode read permitted
0100 user mode write permitted
0010 supervisor mode read permitted
0001 supervisor mode write permitted
The unexpected trap messages indicated in the previous
(CAM test) section may also appear.
VIDC test
It is not possible to monitor the video or sound outputs of
VIDC from within the integral test software. However,
some timing tests are performed on VIDC to check the
proper clock speed (relative to the IOC clock) and to
check the basic operation of the timing generators. The
VIDC tests are announced by the message
VIDC:
The vertical timing interval (should be 20mS) is then
compared with the IOC timer by examining the IOC timer
at two consecutive Virq (VIDC interrupt request) edges. If
the timed value is outside 19.8 - 20.2 ms, a failure will be
indicated with the message
Virq bad xxxxxx
where xxxxxx may be
000001 Failed to find the first Virq, to start timing
00000o Failed to find second Virq within IOC timeout
or either Virq or IOC timeout within
200ms.
other Measured time in microseconds
Failures may be indicated due to either IOC or VIDC
failure or a failure of the Virq interrupt line. An IOC failure
will usually also result in an unusual value of the
measured processor speed.
Similar tests are performed on the sound section of VIDC:
here the 10C timers are set to 10.14 and 10.34 ms. A
sound DMA is then started, with a clock rate and length
which result in completion in 10.24 ms. The Sirq bit in
IOC is tested to ensure that it appears after the expiry of
the first timer and before the expiry of the second.
Failures are indicated by the message
Sirq bad xxxxxx
where xxxxx may be
000001 Timers stuck as though TO done, T1 not
done.
5-8 Issue 2, June 1991 Part 5 - Main PCB fault diagnosis