Service manual

Service Manual
MEMC acts as the interface between the ARM, VIDC,
IOC, ROM (Read-Only Memory) and DRAM (Dynamic
RAM) devices, providing all the critical system timing
signals, including processor clocks.
Up to 4 MB of DRAM is connected to the 'Master'
MEMC which provides all signals and refresh
operations. A Logical to Physical Translator maps the
Physical Memory into a 32 MB Logical address space (
with three levels of protection) allowing Virtual Memory
and Multi-Tasking operations to be implemented. Fast
page mode DRAM accesses are used to maximise
memory bandwidth. VIDC requests data from the RAM
when required and buffers it in one of three FIFOs
before using it. Data is requested in blocks of four 32-bit
words, allowing efficient use of paged-mode DRAM
without locking the system data bus for long periods.
MEMC supports Direct Memory Access (DMA)
operations with a set of programmable DMA Address
Generators which provide a circular buffer for Video
data, a linear buffer for Cursor data and a double buffer
for Sound data.
IOC controls the I/O bus and expansion cards, and
provides basic functions such as the keyboard interface,
system timers, interrupt masks and control registers. It
supports a number of different peripheral cycles and all
I/O accesses are memory mapped.
VIDC takes video data from memory under DMA
control, serialises it and passes it through a colour look-
up palette and converts it to analogue signals for driving
the CRT guns. VIDC also controls all the display timing
parameters and controls the position and pattern of the
cursor sprite. In addition, it incorporates an exponential
Digital to Analogue Converter (DAC) and stereo image
table for the generation of high-quality sound from data
in the DRAM.
VIDC is a highly programmable device, offering a very
wide choice of display formats. The colour look-up
palette which drives the three on-chip DACs is 13 bits
wide, offering a choice from 4096 colours or an external
video source.
The cursor sprite is 32 pixels wide and any number of
rasters high. Three simultaneous colours (again from a
choice of 4096) are supported and any pixel can be
defined as transparent, making possible cursors of
many shapes. It can be positioned anywhere on the
screen. The sound system implemented on the device
can support up to eight channels, each with a separate
stereo position.
Additional memory is provided on daughter cards, in
4MB blocks. Each 4MB block is controlled by a separate
MEMC.
NOTE: MEMCs must be Acorn Part Number 2201,393,
to ensure correct timing parameters.
System timing
Fig 1-2: System timing shows how the various clock
signals are derived for the system.
Fig 1-2: System timing
1-2 Issue 2, June 1991 Part 1 - System description