Service manual

Service Manual
These values will vary between machine types, and the
bus cycle speed will improve when MEMC1 a is fitted.
Note that ARM3 uses an additional clock for cached and
internal operations which is not enabled when this test is
performed.
Large memory test
The earlier memory tests performed brief checks on the
memory control and data lines to ensure that the
memory components were present and to assist in
finding short or open circuits in the interconnections.
Ideally, a large
number of pattern tests should be run to detect possible
pattern sensitivity or obscure bit-failure faults. However,
these take a considerable time to run and are not
suitable for a POST.
The minimum test required is to exercise each RAM
location through zero and one values. The large RAM
test does this, using an odd-repeat-length data pattern to
reduce the possibility that an address/data line short will
be concealed by the test method.
The test code is loaded into RAM for greater speed. For
this reason, the test is not run if a previous test has
detected any fault, since the test code might not then
remain valid for the execution of the test. It is still
possible that an addressing fault undetected by the
address line tests could cause the test code to be
overwritten by the memory test patterns. In this case, the
RAM test announcement
RAM:
would remain on the display without a subsequent
message. If the RAM test is not run due to previously
detected faults, the message
RAM: skipped
will be displayed.
The screen colour changes from purple to blue after the
RAM: message is displayed and before the test
commences.
If the test fails, the failing location is displayed in a
message of the form
RAM Bad xxxxxxx
where xxxxxxx is near the failed location. In the
current version of the software, the value displayed may
be up to 13 words PAST the actual location.
CAM test
The content-addressable-memory used by MEMC to
perform logical to physical address mapping is tested by
this sequence. The test, announced by the message
CAMs:
relies on proper functioning of some memory in order to
store an exception vector. This test is, therefore, not run
unless both the memory control lines and the main
memory test have passed. In this case, the message
CAMs skipped
will be displayed.
Any failure reported by this test (provided that the
memory configuration has been correctly determined:
check the result of the 'M Size' test) probably points to a
failure in MEMC, although a poor connection to MEMC
from the ARM is also possible.
First, the memory is initialised by writing a copy of the
vectors and a unique identifying value to each physical
page (in descending memory address order). The extent
and size of physical pages is determined by the memory
sizing algorithm executed earlier. The highest expected
page is then checked to ensure it hasn't been overwritten
by an address fault when a lower addressed page was
initialized. This check is made at descending addresses
until a correct identifier is found: this is the highest valid
physical memory page and is compared against the
expected number of pages for this memory configuration.
This part of the test may result in an error message of the
form
CAM ## xxx.yyy
meaning that an unexpected number of CAM entries
were found, where xxx is the number expected for the
calculated memory configuration, and yyy is the number
actually found.
The vector in the current page 0 is then checked to
ensure it's still there (in physical memory). The test will
crash if memory is unable to record the vector. Use of the
vector also depends on the proper mapping of logical
page zero to a physical page containing the vectors: this
cannot be checked, since any attempt to test logical page
zero will be forced to use the vector if the memory
mapping has failed, crashing the system.
Failure of the vector data to be retained in physical
memory is indicated by the message
CAM vec xxxxxxxx
where xxxxxxxx is a bitmap indicating which of the data
bits appear to have been lost (1 in a given position
indicates that bit failed to retain the expected data).
Each physical page is then mapped at a series of logical
addresses. To save time, not all logical addresses are
checked — only a short sequence intended to exercise all
the comparators in the CAM array with each bit value.
Mapping is checked by placing the physical page at each
logical address in turn and checking the expected data at
that logical page. It is possible for no page to be mapped
there (causing an abort error), for the wrong page to be
mapped there (causing a data mismatch) and for the
page under test to be simultaneously mapped elsewhere.
This last possibility cannot be exhaustively tested in a
short time, so again a test is made with each of the bits in
the logical page number flipped in turn to test for an
address comparator that always finds a match.
The failures indicated by these tests will almost always
imply a faulty MEMC: the physical page number in the
displayed results may be used to indicate which MEMC in
a multiple-MEMC system is at fault. The physical page
number (in hexadecimal) should be divided by &80 to
indicate the faulty MEMC.
Part 5 - Main PCB fault diagnosis Issue 2, June 1991 5-7