Service manual

Service Manual
Note that the memory sizing algorithm uses address
aliasing to determine the MEMC page size to be used.
This may cause address line faults to result in an
incorrect memory size detection rather than an address
line error.
The ARM memory interface is capable of both word and
byte accesses to memory. These are indistinguishable
when data is read (the whole word is read and the
unused data discarded), but byte write operations must
write only the proper byte without affecting the other
bytes in the same word. This is achieved by using four
byte CAS strobes to indicate which byte is to be written.
All four strobes occur simultaneously for a word write:
thus two strobes shorted together will not be detected by
the word-access memory tests.
The byte strobe lines test is announced by the message
Byte:
and consists of a test (repeated at 4 MB intervals within
the physical memory address space) which, for each of
the four bytes in a word:
• writes a pattern (&AABBCCDD) to the test word
• writes the byte number to the test byte (0 to 3)
• reads back and verifies the modified test word.
If this test fails for any byte strobes at each of four
possible 4 MB address areas, a failure message of the
form
Byte xxxxxxx
will be displayed, where xxxxxxx is the address at
which failure occurred, and the lowest digit is a bitmap of
the failing byte strobes. Thus a failure of the lowest two
byte strobes (CASO, CAS) at the second 4MB memory
region will be indicated by the fault code 2400003.
Finally, if the line tests all pass and there is less than the
(maximum) 16 MB of physical memory fitted, the data
line test is repeated just above where memory ends.
This produces some diagnostic information about data
line faults on expansion memory cards, if such faults
have resulted in a failure of the memory-sizing algorithm
to detect the presence of the expansion card.
This test is announced by the message
Exp?:
and always results in the two displays which indicate
where the memory was tested (this should be just above
the reported memory size) and a bitmap of faulty lines
Exp? @ xxxxxxx Exp? yyyyyyyy
Note that some systems have high-order memory
address lines undecoded. This will result in an image of
good memory 4 MB above the start of real physical
memory. This will have no failing bits, so an expansion
bitmap of 00000000 is displayed rather than the
expected FFFFFFFF.
IOC test
The functions of IOC are not tested in the current release
of the integral test software. However, this stage indicates
the first access to IOC and hence if the announcement
message
IOC:
remains stuck on the display, an IOC addressing problem
is likely to exist. The test does read the IOC interrupt
status registers and display them on the LCD: this may
be used to indicate, for instance, a stuck FIQ line causing
permanent FIQs. No attempt is made to clear pending
IOC interrupts before displaying the status registers. The
status registers are displayed in the form
IOC ccaabbff
where cc is the control register, as is IRQ status register
A, bb is IRQ status register B and ff is the FIQ status
register. The detailed content of these registers is
described in the VL86C010 RISC family data manual.
10 Initialisation
There are a number of 10 registers on Archimedes main
boards in IOC address space. These are initialized to
fixed values to ensure that floppy disc drives, etc are
disabled during the POST.
Register initialization is performed after the
announcement
IOinit:
is displayed. At the current time, the registers are written
as follows:
Address Data Register usage
&3350010 &00 Printer port data
&3350018 &00 FDC control & printer strobes
&3350040 &FF FDD select lines
&3350048 &00 VIDC clock speed selection
Speed test
MEMC has certain configuration possibilities for various
ROM speeds. In order to obtain maximum speed from the
system, the system memory clock speed is measured
and the ROM speed set to ensure the shortest allowed
cycle time. Timing the memory speed is dependant on
proper operation of IOC and a failure will result in a wildly
inaccurate estimate of the system speed. The result of
this timing test is therefore displayed for comparison with
known standards for given machine types.
The test is announced by the message
Speed:
and the results are displayed in the format
Speed xxxx.y.z
where
xxxx is the processor speed (in KHz)
y is 0 for MEMC, 1 for MEMC1a
z is the chosen EPROM speed as written to
the MEMC control register.
5-6 Issue 2, June 1991 Part 5 - Main PCB fault diagnosis