Service manual
Service Manual
reserved for data used to force the CRC of individual
ROMs to be zero. This checksum should always total
zero - if it doesn't, the message
ROM bad xxxxxxxx
(where
xxxxxxxx
is the calculated checksum in
hexadecimal) is displayed. If a faulty checksum is
detected, an additional test is performed to search for a
possible ROM address line fault. This compares the
words at the start of the ROM (&3800000) with data at a
series of walking-one addresses (&3804000, &3808000,
&3810000 etc). If an image of the initial ROM data is
found before the expected end address of the ROM, this
may indicate an address line shorted or not connected to
the ROM. The results of this test are indicated as
ROM size xxxxxx
where xxxxxx is the measured size of the ROM in bytes
of address space used (080000 for 1 Mbit ROMs,
200000 for 4 MBit ROMs) displayed in hexadecimal.
Memory size determination
The algorithm used by RISC OS to determine memory
size and page configuration is also used by the test
software. This algorithm will only operate on working
memory, since it is not possible to distinguish between
faulty memory and not-fitted memory. Use of the same
algorithm ensures that memory faults which cause an
incorrect determination of memory size to be made will
test the memory in the same configuration.
Memory size tests are announced by the message
M Size:
and the result is indicated by the message
M Size xxxx.yy
where xxxx is the measured memory size in KBytes, and
yy is the MEMC page size, also in KBytes. Thus a 4MB
machine (32K pagesize) should indicate
M Size 1000.20
Note that complete memory failure will result in selection
of the smallest permitted memory configuration, 0100.08
(256 Kbyte, 4K page size).
Memory line tests
These tests attempt to exercise address, data and
control lines into the memory array. They are performed
only on the size of memory indicated in the previous
section.
The data line tests are announced by the message
Data:
and perform walking-one and walking-zero tests of the
data lines in attempt to detect stuck-at-one, stuck-at-zero
or tied-together lines. The test is repeated at 1 MB
intervals to exercise all arrays of memory devices, and
consists of a loop which writes
&00000001 to memory at offset 0 from the test
address
&FFFFFFFE
to memory at offset 4 from the test
address
and cycles these patterns through to
&80000000
to memory at offset 248 from the test
address
&7FFFFFFF
to memory at offset 252 from the test
address.
A second loop then validates the patterns, recording as
a bit pattern any data bits which failed to hold the proper
values. If any bits failed, the memory sizing algorithm is
likely to have set the wrong MEMC page size. This can
generate misleading faults, since the highest DRAM
multiplexed address line (RA9) is not driven. In order to
obtain consistent data bit fault diagnosis, the memory
configuration is forced to 32K pagesize. This will cause
address errors, but if data errors area present the
address tests will be meaningless in any case.
A pair of error messages indicating the first address at
which failure occurred and a bitmap of all the failing data
bits is displayed. The messages
Data @ 2000000
Data 00004001
would then indicate that bits DO and D14 showed a fault
at the lowest memory address. Note that this is a
physical memory address, since all memory tests are
performed in the physical address space.
If the data line tests passed an address line test will then
be performed, announced by the message
Addrs:
The test consists of a loop which writes unique data
patterns to pairs of word addresses at memory locations
between the bottom and (previously calculated) top of
physical memory. These locations are again chosen by
walking a one and a zero leftwards through the address
space: thus the test addresses for 1 MB memory will be
2000000 write A5A5A5A5 (test endpoints)
20FFFFC write A5A55A5A
2000004 write 00000004 (bit A2)
20FFFF8 write FFFFFFFB
2000008 write 00000008 (bit A3)
20FFFF4 write FFFFFFF7
...
through to ...
2080000 write 00080000 (bit A19)
207FFFC write FFF7FFFF
The patterns are then checked, and the address bits
which appear to have no effect (ie the same data is read
regardless of whether the address bit tested is one or
zero) are marked in result bitmap. If any such bits are
found, the error message
Addrs xxxxxxx
will be displayed, where xxxxxxx is the resulting fault
bitmap (hence an ineffective bit A8 will result in a fault
display of 000100).
Part 5 - Main PCB fault diagnosis Issue 2, June 1991 5-5